HIGH SPEED DIFFERENTIAL RECEIVERS

SN65LVDS33, SN65LVDT33, SN65LVDS34, SN65LVDT34 HIGH SPEED DIFFERENTIAL RECEIVERS SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004 D 400-Mbps Signaling Rate1 and 200-Mxfr/s D D D D D D D D D D D Data Transfer Rate Operates With a Single 3.3-V Supply −4-V to 5-V Common-Mode Input Voltage Range Differential Input Thresholds <±50 mV With 50 mV of Hysteresis Over Entire Common-Mode Input Voltage Range Integrated 110-Ω Line Termination Resistors On LVDT Products TSSOP Packaging (33 Only) Complies With TIA/EIA-644 (LVDS) Active Failsafe Assures a High-Level Output With No Input Bus-Pin ESD Protection Exceeds 15 kV HBM Input Remains High-Impedance on Power Down TTL Inputs Are 5-V Tolerant Pin-Compatible With the AM26LS32, SN65LVDS32B, µA9637, SN65LVDS9637B SN65LVDS33D SN65LVDT33D SN65LVDS33PW SN65LVDT33PW D OR PW PACKAGE (TOP VIEW) logic diagram (positive logic) G G SN65LVDT33 ONLY 1B 1A 1Y G 2Y 2A 2B GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC 4B 4A 4Y G 3Y 3A 3B 1A 1Y 1B 2A 2B 3A 3B 4A 4B 4Y 3Y 2Y SN65LVDS34D SN65LVDT34D D PACKAGE (TOP VIEW) description This family of four LVDS data line receivers offers the widest common-mode input voltage range in the industry. These receivers provide an input voltage range specification compatible with a 5-V PECL signal as well as an overall increased ground-noise tolerance. They are in industry standard footprints with integrated termination as an option. Precise control of the differential input voltage thresholds allows for inclusion of 50 mV of input voltage hysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no more than ±50 mV over the full input common-mode voltage range. The high-speed switching of LVDS signals usually necessitates the use of a line impedance matching resistor at the receiving-end of the cable or transmission media. The SN65LVDT series of receivers eliminates this external resistor by integrating it with the receiver. The nonterminated SN65LVDS series is also available for multidrop or other termination circuits. VCC 1Y 2Y GND logic diagram (positive logic) 1A 1B 2A 2B 1A 1Y 1B SN65LVDT34 ONLY 1 2 3 4 8 7 6 5 2A 2B 2Y AVAILABLE OPTIONS PART NUMBER† NUMBER TERMINATION OF RESISTOR RECEIVERS 4 4 4 4 2 2 No No Yes Yes No Yes SYMBOLIZATION SN65LVDS33D SN65LVDS33PW SN65LVDT33D SN65LVDT33PW SN65LVDS34D SN65LVDT34D LVDS33 LVDS33 LVDT33 LVDT33 LVDS34 LVDT34 † Add the suffix R for taped and reeled carrier. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1The signalling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second). PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2001 − 2004, Texas Instruments Incorporated WWW.TI.COM 1 SN65LVDS33, SN65LVDT33, SN65LVDS34, SN65LVDT34 HIGH SPEED DIFFERENTIAL RECEIVERS SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004 description (continued) The receivers can withstand ±15 kV human-body model (HBM) and ±600 V machine model (MM) electrostatic discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled and other connections where potentially damaging noise is always a threat. The receivers also include a (patent pending) failsafe circuit that will provide a high-level output within 600 ns after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or powered-down transmitters. The failsafe circuit prevents noise from being received as valid data under these fault conditions. This feature may also be used for Wired-Or bus signaling. See The Active Failsafe Feature of the SN65LVDS32B application note. The intended application and signaling technique of these devices is point-to-point baseband data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. The SN65LVDS33, SN65LVDT33, SN65LVDS34 and SN65LVDT34 are characterized for operation from −40°C to 85°C. Function Tables SN65LVDS33 and SN65LVDT33 DIFFERENTIAL INPUT VID = VA − VB VID ≥ -32 mV −100 mV < VID ≤ −32 mV VID ≤ −100 mV X Open ENABLES G H X H X H X L H X G X L X L X L H X L OUTPUT Y H H ? ? L L Z H H SN65LVDS34 and SN65LVDT34 DIFFERENTIAL INPUT VID = VA − VB VID ≥ -32 mV −100 mV < VID ≤ −32 mV VID ≤ -100 mV Open H = high level, L = low level, ? = indeterminate OUTPUT Y H ? L H H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate 2 WWW.TI.COM SN65LVDS33, SN65LVDT33, SN65LVDS34, SN65LVDT34 HIGH SPEED DIFFERENTIAL RECEIVERS SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004 equivalent input and output schematic diagrams VCC Attenuation Network VCC 1 pF 60 kΩ A Input 200 kΩ 3 pF 250 kΩ 7V 7V 6.5 kΩ Attenuation Network 6.5 kΩ Attenuation Network B Input 7V 7V LVDT Only 110 Ω VCC VCC 300 kΩ (G Only) 100 Ω Enable Inputs 7V 37 Ω Y Output 7V 300 kΩ (G Only) WWW.TI.COM 3 SN65LVDS33, SN65LVDT33, SN65LVDS34, SN65LVDT34 HIGH SPEED DIFFERENTIAL RECEIVERS SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4 V Voltage range: Enables or Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −1 V to 6 V A or B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −5 V to 6 V VA − VB (LVDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 V Electrostatic discharge: A, B, and GND (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . Class 3, A: 15 kV, B: 500 V Charged-device mode: All pins (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±500 V Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. 2. Tested in accordance with JEDEC Standard 22, Test Method A114-A. 3. Tested in accordance with JEDEC Standard 22, Test Method C101. DISSIPATION RATING TABLE PACKAGE D8 PW16 D16 TA ≤ 25°C POWER RATING 725 mW 774 mW 950 mW OPERATING FACTOR‡ ABOVE TA = 25°C 5.8 mW/°C 6.2 mW/°C 7.6 mW/°C TA = 85°C POWER RATING 377 mW 402 mW 494 mW ‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. recommended operating conditions MIN Supply voltage, VCC High-level input voltage, VIH Low-level input voltage, VIL Magnitude of differential input voltage,  VID Enables Enables LVDS LVDT −4 −40 3 2 0 0.1 NOM 3.3 MAX 3.6 5 0.8 3 0.8 5 85 V V °C UNIT V V V Voltage at any bus terminal (separately or common-mode), VI or VIC Operating free-air temperature, TA 4 WWW.TI.COM SN65LVDS33, SN65LVDT33, SN65LVDS34, SN65LVDT34 HIGH SPEED DIFFERENTIAL RECEIVERS SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER VIT1 VIT2 VIT3 VID(HYS) VOH VOL ICC Positive-going differential input voltage threshold Negative-going differential input voltage threshold Differential input failsafe voltage threshold Differential input voltage hysteresis, VIT1 − VIT2 High-level output voltage Low-level output voltage SN65LVDx33 SN65LVDx34 IOH = −4 mA IOL = 4 mA G at VCC, No load, Steady-state G at GND No load, VI = 0 V, VI = 2.4 V, VI = −4 V, VI = 5 V, VI = 0 V, VI = 2.4 V, VI = −4 V, VI = 5 V, VID = 100 mV, VID = 200 mV, Steady-state Other input open Other input open Other input open Other input open Other input open Other input open Other input open Other input open VIC= −4 V or 5 V VIC= −4 V or 5 V 1.55 2.4 0.4 16 1.1 8 23 5 12 ±20 ±20 ±75 ±40 ±40 ±40 ±150 ±80 ±3 2.22 ±20 ±50 ±30 ±100 10 10 −10 VI = 0.4 sin (4E6πt) + 0.5 V 5 10 µA µA µA pF µA A µA mA µA A µA A mA VIB = −4 V or 5 V, See Figures 1 and 2 See Table 1 and Figure 5 −50 −32 50 −100 TEST CONDITIONS MIN TYP† MAX 50 mV mV mV V V UNIT Supply current SN65LVDS II Input current (A or B inputs) SN65LVDT IID Differential input current (IIA − IIB) SN65LVDS SN65LVDT SN65LVDS II(OFF) Power-off input current (A or B inputs) SN65LVDT VA or VB = 0 V or 2.4 V, VCC = 0 V VA or VB = −4 or 5 V, VCC = 0 V VA or VB =0 V or 2.4 V, V