HIGH-SPEED DIFFERENTIAL LINE RECEIVER

SN65LVDT2 HIGH-SPEED DIFFERENTIAL LINE RECEIVER SLLS374B – JULY 1999 – REVISED JANUARY 2000 D D D D D D D D D D D Meets or Exceeds ANSI TIA/EIA-644-1995 Standard Integrated Line Termination Resistor Designed for Signaling Rates up to 400 Mbps Operates From a 2.4-V to 3.6-V Supply Available in the SOT23-5 Package Differential Input Voltage Threshold Less Than 100 mV Propagation Delay Times, 2.5 ns Typical Power Dissipation at 200 MHz is Typically 60 mW Bus-Pin ESD Protection Exceeds 15 kV Open-Circuit Fail Safe Outputs High Impedance With VCC < 1.5 V SN65LVDT2 DBV PACKAGE (TOP VIEW) VCC GND A 1 2 3 4 B 5 R logic diagram A 3 110 Ω B 4 5 R Function Table INPUTS VID = VA – VB VID ≥ 100 mV –100 mV < VID < 100 mV VID ≤ –100 mV Open OUTPUT R H ? L H description The SN65LVDT2 is a single low-voltage differential line receiver in a small-outline transistor package. The inputs comply with the TIA/EIA-644 standard and provide a maximum differential input threshold of 100 mV over an input common-mode voltage range of 0 V to 2.5 V. H = high level, L = low level , ? = indeterminate When used with a low-voltage differential signaling (LVDS) driver (such as the SN65LVDS1) in a point-to-point connection, data or clocking signals can be transmitted over printed-circuit board traces or cables at very high rates with very low electromagnetic emissions and power consumption. The high-speed switching of LVDS signals requires the use of a line impedance matching resistor at the receiving-end of the cable or transmission media. TI offers both the SN65LVDT2, which integrates the terminating resistor for point-to-point applications, and its companion the SN65LVDS2, which requires an external resistor. The packaging, low power, low EMI, high ESD tolerance, and wide supply voltage range make these devices ideal for battery-powered applications. The SN65LVDT2 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000, Texas Instruments Incorporated POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN65LVDT2 HIGH-SPEED DIFFERENTIAL LINE RECEIVER SLLS374B – JULY 1999 – REVISED JANUARY 2000 equivalent input and output schematic diagrams VCC VCC 300 kΩ 300 kΩ 5Ω A Input B Input 7V 7V 7V R Output 110 Ω absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V Voltage range (A, B, or R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC+ 0.5 V Electrostatic discharge: A, B , and GND (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . CLass 3, A:15 kV, B:600 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See dissipation rating table Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential I/O bus voltages are with respect to network ground terminal. 2. Tested in accordance with MIL-STD-883C Method 3015.7. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C† TA = 85°C POWER RATING DBV 385 mW 3.1 mW/°C 200 mW † This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-K) and with no air flow. recommended operating conditions MIN Supply voltage, VCC Magnitude of differential input voltage, VID g ( g ) Common–mode input voltage, VIC (see Figure 6) Operating free–air temperature, TA 2.4 0.1 0 2.4 NOM 3.3 MAX 3.6 0.6 ID * V2 UNIT V V V °C –40 VCC–0.8 85 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LVDT2 HIGH-SPEED DIFFERENTIAL LINE RECEIVER SLLS374B – JULY 1999 – REVISED JANUARY 2000 COMMON-MODE INPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE 2.5 VCC = 3.6 V VIC – Common-Mode Input Voltage – V 2 VCC = 2.7 V 1.5 VCC = 2.4 V 1 0.5 MIN 0 0 0.1 0.2 0.3 0.4 0.5 0.6 |VID|– Differential Input Voltage – V Figure 1. VIC vs VID and VCC electrical characteristics over recommended operating conditions, VCC = 2.4 V to 3 V (unless otherwise noted) PARAMETER VITH+ VITH– VOH VOL ICC II IID II(OFF) Positive-going differential input voltage threshold Negative-going differential input voltage threshold High-level output voltage Low-level output voltage Supply current Input current (A or B inputs) Differential input current (IIA – IIB) Power-off input current (A or B inputs) TEST CONDITIONS See Figure 2 and Table 1 IOH = –8 mA IOL = 8 mA No load, Steady state VI = 0 V VI = 2.4 V or VCC – 0.8 VIA = 0.4 V, VIB = 0 V VIA = 2.4 V, VIB = 2 V VCC = 0 V, VI = 2.4 V, Other input open MIN –100 1.9 2.4 0.25 4 0.4 7 ±40 –2.4 3 3.6 4.4 40 TYP† MAX 100 UNIT mV V V mA µA mA µA † All typical values are at 25°C and with a 2.7-V supply. receiver switching characteristics over recommended operating conditions, VCC = 2.4 V to 3 V (unless otherwise noted) PARAMETER tPLH tPHL tsk(p) tr Propagation delay time, low-to-high-level output Propagation delay time, high-to-low-level output Pulse skew (|tpHL – tpLH|)‡ Output signal rise time CL = 10 pF, F See Figure 3 TEST CONDITIONS MIN 1.4 1.4 TYP† 2.6 2.5 0.1 0.8 MAX 3.6 3.6 0.6 1.4 1.4 UNIT ns ns ns ns ns tf Output signal fall time 0.8 † All typical values are at 25°C and with a 2.7-V. ‡ tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN65LVDT2 HIGH-SPEED DIFFERENTIAL LINE RECEIVER SLLS374B – JULY 1999 – REVISED JANUARY 2000 electrical characteristics over recommended operating conditions, VCC = 3 V to 3.6 V (unless otherwise noted) PARAMETER VITH+ VITH– VOH VOL ICC Positive-going differential input voltage threshold Negative-going differential input voltage threshold High-level output voltage Low-level output voltage Supply current TEST CONDITIONS See Figure 2 and Table 1 IOH = –8 mA IOL = 8 mA No load, Steady state VI = 0 V, Other input open VI = 2.4 V, Other input open VIA = 0.4 V, VIB = 0 V VIA = 2.4 V, VIB = 2 V VCC = 0 V, VI = 2.4 V, Other input open –2.4 3 3.6 4.4 40 mA µA MIN –100 2.4 3 0.25 5 0.4 8 ±40 µA TYP† MAX 100 UNIT mV V V mA II Input current (A or B inputs) IID II(OFF) Differential input current (IIA – IIB) Power-off input current (A or B inputs) † All typical values are at 25°C and with a 3.3-V supply. receiver switching characteristics over recommended operating conditions, VCC = 3 V to 3.6 V (unless otherwise noted) PARAMETER tPLH tPHL tsk(p) tr Propagation delay time, low-to-high-level output Propagation delay time, high-to-low-level output Pulse skew (|tpHL – tpLH|)‡ Output signal rise time CL = 10 pF, F See Figure 3 TEST CONDITIONS MIN 1.4 1.4 TYP† 2.6 2.5 0.1 0.7 MAX 3.1 3.1 0.5 1.1 1.1 UNIT ns ns ns ns ns tf Output signal fall time 0.7 † All typical values are at 25°C and with a 3.3-V. ‡ tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LVDT2 HIGH-SPEED DIFFERENTIAL LINE RECEIVER SLLS374B – JULY 1999 – REVISED JANUARY 2000 PARAMETER MEASUREMENT INFORMATION A V IA ) VIB 2 VIA VIC VIB VID B R VO Figure 2. Receiver Voltage Definitions Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages APPLIED VOLTAGES (V) VIA 1.25 1.15 2.4 2.3 0.1 0 1.5 0.9 2.4 1.8 0.6 0 VIB 1.15 1.25 2.3 2.4 0 0.1 0.9 1.5 1.8 2.4 0 0.6 RESULTING DIFFERENTIAL INPUT VOLTAGE (mV) VID 100 – 100 100 – 100 100 – 100 600 – 600 600 – 600 600 – 600 RESULTING COMMONMODE INPUT VOLTAGE (V) VIC 1.2 1.2 2.35 2.35 0.05 0.05 1.2 1.2 2.1 2.1 0.3 0.3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN65LVDT2 HIGH-SPEED DIFFERENTIAL LINE RECEIVER SLLS374B – JULY 1999 – REVISED JANUARY 2000 PARAMETER MEASUREMENT INFORMATION VID VIA VIB CL 10 pF VO VIA 1.4 V VIB 1V VID 0.4 V 0V – 0.4 V tPHL tPLH VOH 1.4 V 0.4 V tf tr VOH 1.2 V 20% tf tr VOL With VCC = 2.7 V VOL With VCC = 3.3 V VO 2.4 V VO 80% NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. Figure 3. Timing Test Circuit and Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LVDT2 HIGH-SPEED DIFFERENTIAL LINE RECEIVER SLLS374B – JULY 1999 – REVISED JANUARY 2000 TYPICAL CHARACTERISTICS HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 4 3.5 3 2.5 VCC = 2.7 V 2 1.5 1 0.5 0 –60 – 50 – 40 – 30 – 20 – 10 0 0 10 20 30 40 50 60 70 IOH – High-Level Output Current – mA IOL – Low-Level O