DIFFERENTIAL TRANSLATOR/REPEATER

www.ti.com SN65LVDS100, SN65LVDT100 SN65LVDS101, SN65LVDT101 SLLS516C – AUGUST 2002 – REVISED JUNE 2004 DIFFERENTIAL TRANSLATOR/REPEATER FEATURES • • • • • • • • • • • • • • Designed for Signaling Rates ≥ 2 Gbps Total Jitter < 65 ps Low-Power Alternative for the MC100EP16 Low 100 ps (Max) Part-To-Part Skew 25 mV of Receiver Input Threshold Hysteresis Over 0-V to 4-V Common-Mode Range Inputs Electrically Compatible With LVPECL, CML, and LVDS Signal Levels 3.3-V Supply Operation LVDT Integrates 110-Ω Terminating Resistor Offered in SOIC and MSOP (1) DESCRIPTION The SN65LVDS100, SN65LVDT100, SN65LVDS101, and SN65LVDT101 are a high-speed differential receiver and driver connected as a repeater. The receiver accepts low-voltage differential signaling (LVDS), positive-emitter-coupled logic (PECL), or current-mode logic (CML) input signals at rates up to 2 Gbps and repeats it as either an LVDS or PECL output signal. The signal path through the device is differential for low radiated emissions and minimal added jitter. The outputs of the SN65LVDS100 and SN65LVDT100 are LVDS levels as defined by TIA/EIA-644-A. The outputs of the SN65LVDS101 and SN65LVDT101 are compatible with 3.3-V PECL levels. Both drive differential transmission lines with nominally 100-Ω characteristic impedance. The SN65LVDT100 and SN65LVDT101 include a 110-Ω differential line termination resistor for less board space, fewer components, and the shortest stub length possible. They do not include the VBB voltage reference found in the SN65LVDS100 and SN65LVDS101. VBB provides a voltage reference of typically 1.35 V below VCC for use in receiving single-ended input signals and is particularly useful with single-ended 3.3-V PECL inputs. When not used, VBB should be unconnected or open. All devices are characterized for operation from –40°C to 85°C. EYE PATTERN APPLICATIONS 622 MHz Central Office Clock Distribution High-Speed Network Routing Wireless Basestations Low Jitter Clock Repeater Serdes LVPECL Output to FPGA LVDS Input Translator (1) The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second). FUNCTIONAL DIAGRAM SN65LVDS100 and SN65LVDS101 VCC A 8 2 7 6 B 3 Y Z 4 VBB 2 Gbps 223 - 1 PRBS VCC = 3.3 V VID = 200 mV VIC = 1.2 V Vert.Scale= 200 mV/div 1 GHz SN65LVDT100 and SN65LVDT101 2 A 7 110 Ω 6 3 B Y Z Horizontal Scale= 200 ps/div Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002–2004, Texas Instruments Incorporated SN65LVDS100, SN65LVDT100 SN65LVDS101, SN65LVDT101 SLLS516C – AUGUST 2002 – REVISED JUNE 2004 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION OUTPUT LVDS LVDS LVDS LVDS LVPECL LVPECL LVPECL LVPECL (1) TERMINATION RESISTOR No No Yes Yes No No Yes Yes VBB Yes Yes No No Yes Yes No No PART NUMBER (1) SN65LVDS100D SN65LVDS100DGK SN65LVDT100D SN65LVDT100DGK SN65LVDS101D SN65LVDS101DGK SN65LVDT101D SN65LVDT101DGK PART MARKING DL100 AZK DE100 AZL DL101 AZM DE101 BAF PACKAGE SOIC MSOP SOIC MSOP SOIC MSOP SOIC MSOP Add the suffix R for taped and reeled carrier (i.e. SN65LVDS100DR). ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range unless otherwise noted UNIT VCC IBB VI VO VID Supply voltage range (2) VBB Output current Voltage range, (A, B, Y, Z) Differential voltage, |VA– VB| ('LVDT100 and 'LVDT101 only) ESD PD (1) (2) (3) (4) Human Body Model (3) Charged-Device Model (4) Continuous power dissipation A, B, Y, Z, and GND All pins All pins –0.5 V to 4 V ±0.5 mA 0 V to 4.3 V 1V ±5 kV ±2 kV ±1500 V See Dissipation Rating Table Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-A.7. Tested in accordance with JEDEC Standard 22, Test Method C101. POWER DISSIPATION RATINGS PACKAGE DGK D (1) TA ≤ 25°C POWER RATING 377 mW 481 mW DERATING FACTOR (1) ABOVE TA = 25°C 3.8 mW/°C 4.8 mW/°C TA = 85°C POWER RATING 151 mW 192 mW This is the inverse of the junction-to-ambient thermal resistance with no air flow installed on the JESD51-3 low effective thermal conductivity test board for leadless surface mount packages. 2 www.ti.com SN65LVDS100, SN65LVDT100 SN65LVDS101, SN65LVDT101 SLLS516C – AUGUST 2002 – REVISED JUNE 2004 RECOMMENDED OPERATING CONDITIONS MIN NOM Supply voltage, VCC Magnitude of differential input voltage |VID| 'LVDS100 or 'LVDS101 'LVDT100 or 'LVDT101 3 0.1 0.1 0 –400 (1) –40 3.3 MAX UNIT 3.6 1 0.8 4 12 85 V V V µA °C Input voltage (any combination of common-mode or input signals), VI VBB output current, IO(VBB) Operating free-air temperature, TA (1) The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet. ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise specified) PARAMETER ICC Supply current, 'LVDx100 Supply current, 'LVDx101 Device power dissipation, 'LVDx100 PD VBB Device power dissipation, 'LVDx101 Reference voltage output, 'LVDS100 or 'LVDS101 Positive-going differential input voltage threshold Negative-going differential input voltage threshold Input current TEST CONDITIONS No load or input RL = 50 Ω to 1 V, No input RL = 100 Ω, No input Y and Z to VCC - 2 V through 50 Ω, No input IO = –400 µA or 12 µA 116 VCC–1.4 VCC–1.35 MIN TYP (1) MAX 30 61 110 142 VCC–1.3 UNIT mA 25 50 mW mV SN65LVDS100 and SN65LVDS101 INPUT CHARACTERISTICS (see Figure 1) VIT+ VITII 100 See Figure 1 and Table 1 –100 VI = 0 V or 2.4 V, Second input at 1.2 V VI = 4 V, Second input at 1.2 V II(OFF) IIO Ci Power off input current VCC = 1.5 V, VI = 0 V or 2.4 V, Second input at 1.2 V VCC= 1.5 V, VI = 4 V, Second input at 1.2 V VIA = VIB, 0≤ VIA ≤ 4 V VI = 1.2 V –6 0.6 –20 –20 20 33 20 µA 33 6 µA pF µA µA mV Input offset current (|IIA - IIB|) Small-signall input capacitance to GND Positive-going differential input voltage threshold Negative-going differential input voltage threshold Input current SN65LVDT100 and SN65LVDT101 INPUT CHARACTERISTICS (see Figure 1) VIT+ VITII 100 See Figure 1 and Table 1 –100 VI = 0 V or 2.4 V, Other input open VI = 4 V, Other input open VCC = 1.5 V, VI = 0 V or 2.4 V, Other input open VCC= 1.5 V, VI = 4 V, Other input open VID = 300 mV or 500 mV, VIC = 0 V or 2.4 V VCC= 0 V, VID = 300 mV or 500 mV, VIC = 0 V or 2.4 V VI = 1.2 V 90 90 110 110 0.6 –40 –40 40 66 40 µA 66 132 Ω 132 pF µA mV II(OFF) Power off input current R(T) Ci Differential input resistance Small-signall differential input capacitance (1) Typical values are with a 3.3-V supply voltage and room temperature 3 SN65LVDS100, SN65LVDT100 SN65LVDS101, SN65LVDT101 SLLS516C – AUGUST 2002 – REVISED JUNE 2004 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over recommended operating conditions (unless otherwise specified) PARAMETER |VOD| ∆|VOD| VOC(SS) ∆VOC(SS) VOC(PP) IOS IOS(D) Differential output voltage magnitude Change in differential output voltage magnitude between logic states Steady-state common-mode output voltage Change in steady-state common-mode output voltage between logic states Peak-to-peak common-mode output voltage Short-circuit output current Differential short-circuit output current VO(Y) or VO(Z) = 0 V VOD = 0 V 50 Ω to VCC– 2 V, See Figure 4 VCC = 3.3 V, 50-Ω load to 2.3 V 50 Ω to VCC - 2 V, See Figure 4 VCC = 3.3 V, 50-Ω load to 2.3 V 50-Ω load to VCC– 2 V, SeeFigure 4 –24 –12 VCC–1.25 VCC–1.02 2055 1475 475 2280 1690 575 See Figure 3 See Figure 2 TEST CONDITIONS MIN 247 –50 1.125 –50 50 TYP (1) MAX 454 50 1.375 50 150 24 12 VCC–0.9 2405 1775 750 UNIT SN65LVDS100 and SN65LVDT100 OUTPUT CHARACTERISTICS (see Figure 1) 340 mV V mV mV mA mA V mV V mV mV SN65LVDS101 and SN65LVDT101 OUTPUT CHARACTERISTICS (see Figure 1) VOH VOL |VOD| High-level output voltage Low-level output voltage Differential output voltage magnitude VCC–1.83 VCC–1.61 VCC–1.53 SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER tPLH tPHL tr tf tsk(p) Propagation delay time, low-to-high-level output Propagation delay time, high-to-low-level output 'LVDx100 'LVDx101 'LVDx100 'LVDx100 See Figure 5 TEST CONDITIONS MIN TYP (1) MAX 300 400 300 400 470 630 470 630 800 900 800 900 220 220 5 VID = 0.2 V, See Figure 5 1 GHz 50% duty cycle square wave input, VID = 200 mV, VIC = 1.2 V, See Figure 6 2 GHz PRBS, 223–1 run length, VID = 200 mV, VIC = 1.2 V, See Figure 6 2 GHz PRBS, 27–1 run length, VID = 200 mV, VIC = 1.2 V, See Figure 6 1 6 28 17 50 100 3.7