DC TO 4-GBPS DUAL 1:2 MULTIPLEXER/REPEATER/EQUALIZER

www.DataSheet4U.com SN65LVCP40 www.ti.com SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006 DC TO 4-GBPS DUAL 1:2 MULTIPLEXER/REPEATER/EQUALIZER FEATURES • Receiver Equalization and Selectable Driver Preemphasis to Counteract High-Frequency Transmission Line Losses Integration of Two-Serial Port Selectable Loopback Typical Power Consumption 650 mW 30-ps Deterministic Jitter On-Chip 100-Ω Receiver and Driver Differential Termination Resistors Eliminate External Components and Reflection from Stubs 3.3-V Nominal Power Supply • • • • • • • 48-Terminal QFN (Quad Flatpack) 7 mm × 7 mm × 1 mm, 0.5-mm Terminal Pitch Temperature Range: -40°C to 85°C • • • • • APPLICATIONS Bidirectional Link Replicator Signal Conditioner XAUI 802.3ae Protocol Backplane Redundancy Host Adapter (Applications With Internal and External Connection to SERDES) Signaling Rates DC to 4 Gbps Including XAUI, GbE, FC, HDTV • DESCRIPTION The SN65LVCP40 is a signal conditioner and data multiplexer optimized for backplanes. Input equalization and programmable output preemphasis support data rates up to 4 Gbps. Common applications are redundancy switching, signal buffering, or performance improvements on legacy backplane hardware. The SN65LVCP40 combines a pair of 1:2 buffers with a pair of 2:1 multiplexers (mux). Selectable switch-side loopback supports system testing. System interconnects and serial backplane applications of up to 4 Gbps are supported. Each of the two independent channels consists of a transmitter with a fan-out of two, and a receiver with a 2:1 input multiplexer. The drivers provide four selectable levels of preemphasis to compensate for transmission line losses. The receivers incorporates receive equalization and compensates for input transmission line loss. This minimizes deterministic jitter in the link. The equalization is optimized to compensate for a FR-4 backplane trace with 5-dB, high-frequency loss between 375 MHz and 1.875 GHz. This corresponds to a 24-inch long FR-4 trace with 6-mil trace width. This device operates from a single 3.3-V supply. The device has integrated 100-Ω line termination and provides self-biasing. The input tolerates most differential signaling levels such as LVDS, LVPECL or CML. The output impedance matches 100-Ω line impedance. The inputs and outputs may be ac coupled for best interconnectivity with other devices such as SERDES I/O or additional XAUI multiplexer buffer. With ac coupling, jitter is the lowest. FUNCTIONAL DIAGRAM Input Equalization Opens up Data Eye Programmable Preemphasis EQ Input Data After Long Backplane Trace out Output Data SN65LVCP40 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2006, Texas Instruments Incorporated SN65LVCP40 www.ti.com SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The SN65LVCP40 is packaged in a 7 mm × 7 mm × 1 mm QFN (quad flatpack no-lead) lead-free package, and is characterized for operation from -40°C to 85°C. AVAILABLE OPTIONS TA -40°C to 85°C (1) DESCRIPTION Serial multiplexer PACKAGED DEVICE (1) RGZ (48 pin) SN65LVCP40 The package is available taped and reeled. Add an R suffix to device types (e.g., SN65LVCP40RGZR). ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT VCC Supply voltage range (2) Voltage range ESD TJ (1) (2) (3) (4) Human Body Model (3) Charged-Device Model (4) Control inputs, all outputs Receiver inputs All pins All pins –0.5 V to 6 V –0.5 V to (VCC + 0.5 V) –0.5 V to 4 V 4 kV 500 V See Package Thermal Characteristics Table Maximum junction temperature Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-A. Tested in accordance with JEDEC Standard 22, Test Method C101. PACKAGE THERMAL CHARACTERISTICS PACKAGE THERMAL CHARACTERISTICS (1) θJA (junction-to-ambient) θJB (junction-to-board) θJC (junction-to-case) PSI-jt (junction-to-top pseudo) PSI-jb (junction-to-board pseudo) θJP (junction-to-pad) (1) 4-layer JEDEC Board (JESD51-7) using eight GND-vias Ø-0.2 on the center pad as shown in the section: Recommended pcb footprint with boundary and environment conditions of JEDEC Board (JESD51-2) NOM 33 20 23.6 0.6 19.4 5.4 UNIT °C/W °C/W °C/W °C/W °C/W °C/W See application note SPRA953 for a detailed explanation of thermal parameters (http://www-s.ti.com/sc/psheets/spra953/spra953.pdf). 2 Submit Documentation Feedback SN65LVCP40 www.ti.com SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006 RECOMMENDED OPERATING CONDITIONS MIN dR VCC VCC(N) TJ TA Operating data rate Supply voltage Supply voltage noise amplitude Junction temperature Operating free-air temperature (1) dR(in) ≤ 1.25 Gbps 1.25 Gbps < dR(in) ≤ 3.125 Gbps dR(in) > 3.125 Gbps VICM Receiver common-mode input voltage Note: for best jitter performance ac coupling is recommended. -40 100 100 100 1.5 10 Hz to 2 GHz 3.135 3.3 NOM MAX 4 3.465 20 125 85 1750 1560 1000 |V | ID 1.6 VCC * 2 UNIT Gbps V mV °C °C mVpp mVpp mVpp V DIFFERENTIAL INPUTS VID Receiver peak-to-peak differential input voltage (2) CONTROL INPUTS VIH VIL RL (1) (2) High-level input voltage Low-level input voltage Differential load resistance 2 –0.3 80 100 VCC + 0.3 0.8 120 V V Ω DIFFERENTIAL OUTPUTS Maximum free-air temperature operation is allowed as long as the device maximum junction temperature is not exceeded. Differential input voltage VID is defined as | IN+ – IN– |. ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER DIFFERENTIAL INPUTS VIT+ VIT– A(EQ) RT(D) VBB R(BBDC) R(BBAC) Positive going differential input high threshold Negative going differential input low threshold Equalizer gain Termination resistance, differential Open-circuit Input voltage (input self-bias voltage) Biasing network dc impedance Biasing network ac impedance 375 MHz 1.875 GHz RL = 100 Ω±1%, PRES_1 = PRES_0=0; PREL_1 = PREL_0=0; 4 Gbps alternating 1010-pattern; Figure 1 AC-coupled inputs From 375 MHz to 1.875 GHz 80 –50 5 100 1.6 30 42 8.4 650 –650 1000 1300 1.65 See Figure 6 1 1500 120 50 mV mV dB Ω V kΩ Ω TEST CONDITIONS MIN TYP (1) MAX UNIT DIFFERENTIAL OUTPUTS VOH VOL VODB(PP) VOCM ∆VOC(SS) High-level output voltage Low-level output voltage Output differential voltage without preemphasis (2) Output common mode voltage Change in steady-state common-mode output voltage between logic states mVpp mVpp mVpp V mV (1) (2) All typical values are at TA = 25°C and VCC = 3.3 V supply unless otherwise noted. They are for reference purposes and are not production tested. Differential output voltage V(ODB) is defined as | OUT+ – OUT– |. Submit Documentation Feedback 3 SN65LVCP40 www.ti.com SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER Output preemphasis voltage ratio, V(PE) V ODB(PP) TEST CONDITIONS PREx_1:PREx_0 = 00 RL = 100 Ω ±1%; x = L or S; See Figure 1 PREx_1:PREx_0 = 01 PREx_1:PREx_0 = 10 PREx_1:PREx_0 = 11 Output preemphasis is set to 9 dB during test PREx_x = 1; Measured with a 100-MHz clock signal; RL = 100 Ω, ±1%, See Figure 2 Differential on-chip termination between OUT+ and OUT– VIN = VCC VIN = GND MIN TYP (1) 0 3 6 9 MAX UNIT dB VODPE(PP) t(PRE) Preemphasis duration measurement Output resistance 175 ps ro 100 Ω CONTROL INPUTS IIH IIL R(PU) PD ICC High-level Input current Low-level Input currentn Pullup resistance Device power dissipation Device current consumption All outputs terminated 100 Ω All outputs terminated 100 Ω PRBS 27-1 pattern at 4 Gbps 5 90 35 650 880 254 125 µA µA kΩ mW mA POWER CONSUMPTION SWITCHING CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER MULTIPLEXER t(SM) Multiplexer switch time Low-to-high propagation delay High-to-low propagation delay Rise time Fall time Pulse skew, | tPHL– tPLH | (2) Output skew (3) All outputs terminated with 100 Ω See Figure 7for test circuit. BERT setting 10–15 Alternating 10-pattern. 25 Part-to-part skew (4) Device random jitter, rms 0.8 Multiplexer or loopback control to valid output 3 6 ns DIFFERENTIAL OUTPUTS tPLH tPHL tr tf tsk(p) tsk(o) tsk(pp) RJ (1) (2) (3) (4) Propagation delay input to output See Figure 4 20% to 80% of VO(DB); Test Pattern: 100-MHz clock signal; See Figure 3 and Figure 7 0.5 0.5 80 80 20 200 500 2 1 1 ns ns ps ps ps ps ps ps-rms TEST CONDITIONS MIN TYP (1) MAX UNIT All typical values are at 25°C and with 3.3 V supply unless otherwise noted. tsk(p) is the magnitude of the time difference between the tPLH and tPHL of any output of a single device. tsk(o) is the magnitude of the time difference between the tPLH and tPHL of any two outputs of a single device. tsk(pp) is the magnitude