2x2 LVPECL Crosspoint switch

www.DataSheet4U.com SN65LVCP23 www.ti.com SLLS554C − NOVEMBER 2002 − REVISED SEPTEMBER 2004 2x2 LVPECL CROSSPOINT SWITCH FEATURES D High Speed 2x2 LVPECL Crosspoint Switch D LVDS Crosspoint Switch Available in SN65LVCP22 DESCRIPTION The SN65LVCP23 is a 2x2 LVPECL crosspoint switch. The dual channels incorporate wide common-mode (0 V to 4 V) receivers, allowing for the receipt of LVDS, LVPECL, and CML signals. The dual outputs are LVPECL drivers to provide high-speed operation. The SN65LVCP23 provides a single device supporting 2:2 buffering (repeating), 1:2 splitting, 2:1 multiplexing, 2x2 switching, and LVDS/CML to LVPECL level translation on each channel. The flexible operation of the SN65LVCP23 provides a single device to support the redundant serial bus transmission needs (working and protection switching cards) of fault-tolerant switch systems found in optical networking, wireless infrastructure, and data communications systems. TI offers an additional gigibit repeater/ translator in the SN65LVDS101. The SN65LVCP23 uses a fully differential data path to ensure low-noise generation, fast switching times, low pulse width distortion, and low jitter. Output channel-to-channel skew is less than 10 ps (typ) and 50 ps (max) to ensure accurate alignment of outputs in all applications. Both SOIC and TSSOP package options are available. OUTPUTS OPERATING SIMULTANEOUSLY 1.3 Gbps 223 −1 PRBS D 50 ps (Typ), of Peak-to-Peak Jitter With PRBS = 223–1 Pattern (Typ), 50 ps (Max) D Output (Channel-to-Channel) Skew Is 10 ps D Configurable as 2:1 Mux, 1:2 Demux, Repeater or 1:2 Signal Splitter D Inputs Accept LVDS, LVPECL, and CML Signals D D D D Fast Switch Time of 1.7 ns (Typ) Fast Propagation Delay of 0.75 ns (Typ) 16 lead SOIC and TSSOP Packages Operating Temperature: −40°C to 85°C APPLICATIONS D Gigabit Ethernet Redundant Transmission Paths D Gigabit Interface Converters (GBICs) D Fibre Channel Redundant Transmission Paths OUTPUT 1 D D D D D D HDTV Video Routing Base Stations Protection Switching for Serial Backplanes Network Switches/Routers Optical Networking Line Cards/Switches Clock Distribution VCC = 3.3 V |VID| = 200 mV, VIC = 1.2 V Vertical Scale = 400 mV/div OUTPUT 2 650 MHz Horizontal Scale = 200 ps Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2002−2003, Texas Instruments Incorporated SN65LVCP23 www.ti.com SLLS554C − NOVEMBER 2002 − REVISED SEPTEMBER 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION PACKAGE DESIGNATOR SOIC TSSOP PART NUMBER(1) SN65LVCP23D SN65LVCP23PW SYMBOLIZATION LVCP23 LVCP23 (1) Add the suffix R for taped and reeled carrier PACKAGE DISSIPATION RATINGS PACKAGE SOIC (D) CIRCUIT BOARD MODEL High-K(2) High-K(2) TA ≤ 25°C POWER RATING 1361 mW DERATING FACTOR(1) ABOVE TA = 25°C 13.9 mW/°C TA = 85°C POWER RATING 544 mW TSSOP (PW) 1074 mW 10.7 mW/°C 430 mW (1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. (2) In accordance with the High-K thermal metric definitions of EIA/JESD51-7. THERMAL CHARACTERISTICS PARAMETER θJB θJC PD D Junction-to-board thermal resistance Junction-to-case thermal resistance Device power dissipation PW D PW Typical Maximum VCC = 3.3−V, TA = 25°C, 2 Gbps VCC = 3.6−V, TA = 85°C, 2 Gbps TEST CONDITIONS VALUE 15.7 22.1 26.1 17.3 165 234 UNITS °C/W °C/W °C/W °C/W mW mW FUNCTION TABLE SEL0 0 0 1 1 SEL1 0 1 0 1 OUT0 IN0 IN0 IN1 IN1 OUT1 IN0 IN1 IN0 IN1 FUNCTION 1:2 Splitter Repeater Switch 1:2 Splitter FUNCTIONAL BLOCK DIAGRAM OUT 0 OUT 1 EN 0 EN 1 SEL 1 SEL 0 0 1 0 1 IN 0 IN 1 2 SN65LVCP23 www.ti.com SLLS554C − NOVEMBER 2002 − REVISED SEPTEMBER 2004 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS INPUTS IN + IN − VCC 400 Ω SEL, EN 7V 7V 300 kΩ 7V OUTPUTS VCC R VCC VCC R R OUT + VCC 7V OUT − 7V 3 SN65LVCP23 www.ti.com SLLS554C − NOVEMBER 2002 − REVISED SEPTEMBER 2004 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) UNITS Supply voltage(2) range, VCC CMOS/TTL input voltage (ENO, EN1, SEL0, SEL1) Receiver Input voltage (IN+, IN−) LVPECL driver output voltage (OUT+, OUT−) Continuous Output current Storage temperature range Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds Continuous power dissipation Electrostatic discharge Human body model(3) Charged-device mode(4) All pins All pins Surge −0.5 V to 4 V −0.5 V to 4 V −0.7 V to 4.3 V −0.5 V to 4 V 50 mA 100 mA −65°C to 125°C 235°C See Dissipation Rating Table ±5 kV ±500 V (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminals. (3) Tested in accordance with JEDEC Standard 22, Test Method A114-A. (4) Tested in accordance with JEDEC Standard 22, Test Method C101. RECOMMENDED OPERATING CONDITIONS MIN Supply voltage, VCC Receiver input voltage Junction temperature Operating free-air temperature, TA(1) −40 Magnitude of differential input voltage |VID| 0.1 (1) Maximum free-air temperature operation is allowed as long as the device maximum junction temperature is not exceeded. 3 0 NOM 3.3 MAX UNIT 3.6 4 125 85 3 V V °C °C V 4 SN65LVCP23 www.ti.com SLLS554C − NOVEMBER 2002 − REVISED SEPTEMBER 2004 INPUT ELECTRICAL CHARACTERISTICS over recommended operatingconditions unless otherwise noted PARAMETER CMOS/TTL DC SPECIFICATIONS (EN0, EN1, SEL0, SEL1) VIH VIL IIH IIL High-level input voltage Low-level input voltage High-level input current Low-level input current VIN = 3.6 V or 2.0 V, Vcc = 3.6 V VIN = 0.0 V or 0.8 V, Vcc = 3.6 V ICL = −18 mA RL = 50 Ω to VTT; VTT = VCC − 2.0 V, See Figure 2 VI = 0.4 sin(4E6πt) + 0.5 V See Figure 1 and Table 1 See Figure 1 and Table 1 VID = 100 mV, VCC = 3.0 V to 3.6 V VIN = 4 V, VCC = 3.6 V or 0.0 VIN = 0V, VCC = 3.6V or 0.0 VI = 0.4 sin (4E6πt) + 0.5 V No load −100 25 0.05 ±1 ±1 1 50 65 3.95 ±10 ±10 VCC − 1.3 VCC − 2.2 600 800 3 100 2 GND ±3 ±1 −0.8 VCC 0.8 ±20 ±10 −1.5 VCC − 0.85 VCC − 1.65 1000 V V µA µA V TEST CONDITIONS MIN TYP(1) MAX UNIT VCL Input clamp voltage LVPECL OUTPUT SPECIFICATIONS (OUT0, OUT1) VOH VOL Output high voltage Output low voltage Differential output voltage V mV pF mV mV mV VOD CO Differential output capacitance RECEIVER DC SPECIFICATIONS (IN0, IN1) VTH VTL Positive-going differential input voltage threshold Negative-going differential input voltage threshold VID(HYS) Differential input voltage hysteresis VCMR IIN Common-mode voltage range Input current V µA A pF mA CIN Differential input capacitance SUPPLY CURRENT ICCD DC supply current (1) All typical values are at 25°C and with a 3.3 V supply. 5 SN65LVCP23 www.ti.com SLLS554C − NOVEMBER 2002 − REVISED SEPTEMBER 2004 SWITCHING CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER tSET tHOLD Input to SEL setup time Input to SEL hold time Figure 5 Figure 5 Figure 5 Figure 4 Figure 4 Figure 3 Figure 3 VID = 200 mV, 50% duty cycle, VCM = 1.2 V, 650 MHz VID = 200 mV, PRBS = 223−1 data pattern and K28.5 (0011111010), VCM = 1.2 V at 1.3 Gbps VID = 200 mV, 50% duty cycle, VCM = 1.2 V, 650 MHz VCC = 3.3 V, TA = 25°C, See Figure 3 VCC = 3.3 V, TA = 25°C, See Figure 3 Figure 3 Figure 3 400 400 80 80 TEST CONDITIONS MIN 1 1.1 TYP 0.5 0.5 1.7 2 2 110 110 15 2.5 2.5 2.5 220 220 30 MAX UNIT ns ns ns ns ns ps ps ps tSWITCH SEL to switched output tPHKL Disable time, high-level-to-known LOW tPKLH tLHT tHLT Enable time, known LOW-to-high-level output Differential output signal rise time (20%−80%)(1) Differential output signal fall time (20%−80%)(1) tJIT Added peak−to-peak jitter 50 100 ps tJrms tPLHD tPHLD tskew tCCS Added random jitter (rms) Propagation delay time, low-to-high-level output(1) Propagation delay time, high-to-low-level output(1) Pulse skew (|tPLHD − tPHLD|)(2) Output channel-to-channel skew, splitter mode. 0.3 750 750 20 10 0.5 1100 1100 100 50 psRMS ps ps ps ps fMAX Maximum operating frequency(3) 1 GHz (1) Input: VIC = 1.2 V, VID = 200 mV, 50% duty cycle, 1 MHz, tr/tf = 500 ps (2) tskew is the magnitude of the time difference between the tPLHD and tPHLD of any output of a single device. (3) Signal generator conditions: 50% duty cycle, tr or tf  100 ps (10% to 90%), transmitter output criteria: duty cycle = 45% to 55% VOD  300 mV. PIN ASSIGNMENTS D or PW PACKAGE (TOP VIEW) SEL1 SEL0 IN0+ IN0− VCC IN1+ IN1− VCC 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 EN0 EN1 OUT0+ OUT0− GND OUT1+ OUT1− GND 6 SN65LVCP23 www.ti.com SLLS554C − NOVEMBER 2002 − REVISED SEPTEMBER 2004 PARAMETER MEASUREMENT INFORMATION IIN+ IN+ VIN+ VID IN− IIN− OUT − VOZ OUT + VOD IN+ +IN− 2 VIC VOY VOUT++VOUT− 2 VIN− Figure 1. Voltage and Current Definitions Y Driver Device Z 50 Ω 50 Ω VOD Receiver Device VTT = VCC −2 V Figure 2. Typical Termination for LVPECL Output Driver IN+ VID VIN+ IN− VIN− OUT− VOUT− OUT+ 1 pF VOUT+ VOD 50 Ω VTT 50 �