2 X 2 1000 MBPS LVDS CROSSPOINT SWITCH

www.DataSheet4U.com SN65LVCP22 www.ti.com SLLS553B – NOVEMBER 2002 – REVISED JUNE 2003 2x2 LVDS CROSSPOINT SWITCH FEATURES • • • • • • • • • • • • • • • • • • • High Speed (>1000 Mbps) Upgrade for DS90CP22 2x2 LVDS Crosspoint Switch LVPECL Crosspoint Switch Available in SN65LVCP23 Low-Jitter Fully Differential Data Path 50 ps (Typ), of Peak-to-Peak Jitter With PRBS = 223–1 Pattern Less Than 200 mW (Typ), 300 mW (Max) Total Power Dissipation Output (Channel-to-Channel) Skew Is 10 ps (Typ), 50 ps (Max) Configurable as 2:1 Mux, 1:2 Demux, Repeater or 1:2 Signal Splitter Inputs Accept LVDS, LVPECL, and CML Signals Fast Switch Time of 1.7 ns (Typ) Fast Propagation Delay of 0.65 ns (Typ) 16 Lead SOIC and TSSOP Packages Inter-Operates With TIA/EIA-644-A LVDS Standard Operating Temperature: –40°C to 85°C DESCRIPTION The SN65LVCP22 is a 2×2 crosspoint switch providing greater than 1000 Mbps operation for each path. The dual channels incorporate wide common-mode (0 V to 4 V) receivers, allowing for the receipt of LVDS, LVPECL, and CML signals. The dual outputs are LVDS drivers to provide low-power, low-EMI, high-speed operation. The SN65LVCP22 provides a single device supporting 2:2 buffering (repeating), 1:2 splitting, 2:1 multiplexing, 2×2 switching, and LVPECL/CML to LVDS level translation on each channel. The flexible operation of the SN65LVCP22 provides a single device to support the redundant serial bus transmission needs (working and protection switching cards) of fault-tolerant switch systems found in optical networking, wireless infrastructure, and data commu- nications systems. TI offers additional gigibit repeater/ translator and crosspoint products in the SN65LVDS100 and SN65LVDS122. The SN65LVCP22 uses a fully differential data path to ensure low-noise generation, fast switching times, low pulse width distortion, and low jitter. Output channel-to- channel skew is less than 10 ps (typ) and 50 ps (max) to ensure accurate alignment of outputs in all applications. Both SOIC and TSSOP package options are available to allow easy upgrade for existing solutions, and board area savings where space is critical. OUTPUTS OPERATING SIMULTANEOUSLY 1 Gbps 223 -1 PRBS OUTPUT 1 VCC = 3.3 V |VID| = 200 mV, VIC = 1.2 V Vertical Scale = 200 mV/div OUTPUT 2 500 MHz APPLICATIONS Base Stations Add/Drop Muxes Protection Switching for Serial Backplanes Network Switches/Routers Optical Networking Line Cards/Switches Clock Distribution Horizontal Scale = 300 ps Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002–2003, Texas Instruments Incorporated SN65LVCP22 SLLS553B – NOVEMBER 2002 – REVISED JUNE 2003 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION PACKAGE DESIGNATOR SOIC TSSOP (1) PART NUMBER (1) SN65LVCP22D SN65LVCP22PW SYMBOLIZATION LVCP22 LVCP22 Add the suffix R for taped and reeled carrier PACKAGE DISSIPATION RATINGS PACKAGE SOIC (D) TSSOP (PW) (1) (2) CIRCUIT BOARD MODEL High-K (2) High-K (2) TA ≤ 25°C POWER RATING 1361 mW 1074 mW DERATING FACTOR (1) ABOVE TA = 25°C 13.9 mW/°C 10.7 mW/°C TA = 85°C POWER RATING 544 mW 430 mW This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. In accordance with the High-K thermal metric definitions of EIA/JESD51-7. THERMAL CHARACTERISTICS PARAMETER θJB θJC PD Junction-to-board thermal resistance Junction-to-case thermal resistance Device power dissipation D PW D PW Typical Maximum VCC = 3.3 V, TA = 25°C, 1 Gbps VCC = 3.6 V, TA = 85°C, 1 Gbps TEST CONDITIONS VALUE 11.2 18.4 23.7 16.0 198 313 UNITS °C/W °C/W mW FUNCTION TABLE SEL0 0 0 1 1 SEL1 0 1 0 1 OUT0 IN0 IN0 IN1 IN1 OUT1 IN0 IN1 IN0 IN1 FUNCTION 1:2 Splitter Repeater Switch 1:2 Splitter FUNCTIONAL BLOCK DIAGRAM OUT 0 OUT 1 EN 0 EN 1 SEL 1 SEL 0 0 1 0 1 IN 0 IN 1 2 Submit Documentation Feedback www.ti.com SN65LVCP22 SLLS553B – NOVEMBER 2002 – REVISED JUNE 2003 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS INPUTS VCC IN + IN - 400 Ω SEL, EN 7V 7V 300 kΩ 7V OUTPUTS VCC OUT + OUT - 7V 7V ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) UNITS Supply voltage (2) range, VCC CMOS/TTL input voltage (ENO, EN1, SEL0, SEL1) LVDS receiver input voltage (IN+, IN–) LVDS driver output voltage (OUT+, OUT–) LVDS output short circuit current Storage temperature range Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds Continuous power dissipation Electrostatic discharge (1) (2) (3) (4) Human body model (3) Charged-device mode (4) All pins All pins –0.5 V to 4 V –0.5 V to 4 V –0.7 V to 4.3 V –0.5 V to 4 V Continuous –65°C to 125°C 235°C See Dissipation Rating Table ±5 kV ±500 V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminals. Tested in accordance with JEDEC Standard 22, Test Method A114-A. Tested in accordance with JEDEC Standard 22, Test Method C101. Submit Documentation Feedback 3 SN65LVCP22 SLLS553B – NOVEMBER 2002 – REVISED JUNE 2003 www.ti.com RECOMMENDED OPERATING CONDITIONS MIN Supply voltage, VCC Receiver input voltage Junction temperature Operating free-air temperature, TA (1) Magnitude of differential input voltage |VID| (1) –40 0.1 3 0 NOM MAX 3.3 3.6 4 125 85 3 UNIT V V °C °C V Maximum free-air temperature operation is allowed as long as the device maximum junction temperature is not exceeded. INPUT ELECTRICAL CHARACTERISTICS over recommended operatingconditions unless otherwise noted PARAMETER CMOS/TTL DC SPECIFICATIONS (EN0, EN1, SEL0, SEL1) VIH VIL IIH IIL VCL High-level input voltage Low-level input voltage High-level input current Low-level input current Input clamp voltage VIN = 3.6 V or 2.0 V, VCC = 3.6 V VIN = 0.0 V or 0.8 V, VCC = 3.6 V ICL = –18 mA RL = 75 Ω, See Figure 2 |VOD| ∆|VOD| VOS ∆VOS VOC(PP) IOZ IOFF IOS IOSB CO VTH VTL VCMR IIN CIN Differential output voltage Change in differential output voltage magnitude between logic states Steady-state offset voltage Change in steady-state offset voltage between logic states Peak-to-peak common-mode output voltage High-impedance output current Power-off leakage current Output short-circuit current Both outputs short-circuit current Differential output capacitance Positive-going differential input voltage threshold Negative-going differential input voltage threshold Common-mode voltage range Input current Differential input capacitance RL = 75 Ω, VCC = 3.3 V, TA = 25°C, See Figure 2 VID = ±100 mV, See Figure 2 See Figure 3 See Figure 3 See Figure 3 VOUT = GND or VCC VCC = 0 V, 1.5 V; VOUT = 3.6 V or GND VOUT+ or VOUT- = 0 V VOUT+ and VOUT- = 0 V VI = 0.4 sin(4E6πt) + 0.5 V See Figure 1 and Table 1 See Figure 1 and Table 1 VID = 100 mV, VCC = 3.0 V to 3.6 V VIN = 4 V, VCC = 3.6 V or 0.0 VIN = 0 V, VCC = 3.6V or 0.0 VI = 0.4 sin (4E6πt) + 0.5 V RL = 75 Ω, CL = 5 pF, 500 MHz (1000 Mbps), EN0=EN1=High EN0 = EN1 = Low –100 25 0.05 ±1 ±1 3 3.95 ±10 ±10 –12 3 100 270 285 –25 1 –25 50 1.2 2 GND ±3 ±1 -0.8 365 365 VCC 0.8 ±20 ±10 -1.5 475 440 25 1.45 25 150 ±10 ±10 -24 12 mV V V µA µA V TEST CONDITIONS MIN TYP (1) MAX UNIT LVDS OUTPUT SPECIFICATIONS (OUT0, OUT1) mV V mV mV µA µA mA mA pF mV mV mV V µA pF LVDS RECEIVER DC SPECIFICATIONS (IN0, IN1) VID(HYS) Differential input voltage hysteresis SUPPLY CURRENT ICCD ICCZ (1) Total supply current 3-state supply current All typical values are at 25°C and with a 3.3-V supply. 60 25 87 35 mA mA 4 Submit Documentation Feedback www.ti.com SN65LVCP22 SLLS553B – NOVEMBER 2002 – REVISED JUNE 2003 SWITCHING CHARACTERISTICS over recommended operating conditions unless otherwise noted parameter tSET tHOLD tSWITCH tPHZ tPLZ tPZH tPZL tLHT tHLT Input to SEL setup time Input to SEL hold time SEL to switched output Disable time, high-level-to-high-impedance Disable time, low-level-to-high-impedance Enable time, high-impedance -to-high-level output Enable time, high-impedance-to-low-level output Differential output signal rise time (20%-80%) (1) Differential output signal fall time (20%-80%) (1) TEST CONDITIONS See Figure 6 See Figure 6 See Figure 6 See Figure 5 See Figure 5 See Figure 5 See Figure 5 CL = 5 pF, See Figure 4 CL = 5 pF, See Figure 4 VID = 200 mV, 50% duty cycle, VCM = 1.2 V, 500 MHz, CL = 5 pF VID = 200 mV, PRBS = 223-1 data pattern, VCM = 1.2 V at 1000 Mbps, CL = 5 pF VID = 200 mV, 50% duty cycle, VCM = 1.2 V at 500 MHz, CL = 5 pF 400 400 CL = 5 pF, See Figure 4 CL = 5 pF, See Figure 4 1 output (1) 150 150 MIN 1 1.1 TYP 0.5 0.5 1.7 2 2 2 2 280 280 20 50 1.1 650 650 20 10 2.5 4 4 4 4 450 450 40 105 1.8 1000 1000 100 50 MAX UNIT ns ns ns ns ns ns ns ps ps ps ps psRMS ps ps ps ps GHz tJIT Added peak-to-peak jitter tJrms tPLHD tPHLD tskew tCCS fMAX (1) (2) (3) Added random jitter (rms) Propagation delay time, low-to-high-level output (1) Propagation delay time, high-to-low-level Pulse skew (|tPLHD– tPHLD|) (2) Output cha