ControlNet TM TRANSCEIVER

www.DataSheet4U.com SN65HVD61 www.ti.com SLLS770A – JANUARY 2007 – REVISED FEBRUARY 2007 ControlNet™ TRANSCEIVER FEATURES • • • • • • • • • • • • • Compatible With the ControlNet Standard I/O Operates From 2.5-V to 5-V Supply Receiver thresholds within –120mV to 120mV Receiver hysteresis >50mV Low Power Standby Mode Thermal Shutdown Protection Power-Up/Down Glitch-free Bus Inputs and Outputs Short-Circuit Protection on Outputs RoHS Compliant ControlNet Vendor ID 806 The third signal receiver function (SIG) provides a scaled analog output which is proportional to the differential voltage between XF1 and XF3. This output can be used for diagnostic purposes. FUNCTIONAL DIAGRAM VDD 3 1 RX Vcc 14 2 CD 4 8 SIG -+ 0.1 -+ APPLICATIONS Industrial Networks Programmable Controllers Industrial Drives CHEN DESCRIPTION The SN65HVD61 is designed to meet the requirements for the driver and receiver circuitry of the ControlNet coaxial-based physical layer. These devices are single-channel circuits with one transceiver for single node operation or distributed stand-alone applications. The pull-or-pull transmitter circuit is designed to sink current from a center-tapped transformer, providing galvanic isolation from the shared bus. These devices incorporate a differential receiver (RX) with the 120 mV sensitivity needed by ControlNet industrial applications. A secondary receiver (CD) detects the presence of a valid positive differential signal. TX TXEN TX 5 TSD 7 6 12 XF1 10 XF3 9 DGND 11, 13 CGND RX CD CHEN ControlNet MAC TXEN TX TXBAR HVD61 ControlNet Bus Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. ControlNet is a trademark of ControlNet International, Ltd. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated SN65HVD61 SLLS770A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION PART NUMBER SN65HVD61 (1) R suffix indicates tape and reel PACKAGE D DR (1) MARKED AS 65HVD61 ABSOLUTE MAXIMUM RATINGS (1) VALUE VCC VDD Supply voltage (2) (3) – 0.3 to 6 –0.3 to 6 –0.5 to 6 –22 to +22 –20 to 20 Internally limited ±15 Human Body Model (4) Electrostatic discharge Charged Device Model Machine Model TJ (1) (2) (3) (4) (5) (6) (7) Junction temperature (see (7) (6) (5) UNIT V V V V mA mA kV kV V V °C Supply voltage (4) Logic input voltage range (TX, TXBAR , TXEN, CHEN) Bus terminal voltage range (XF1, XF3) Logic input current, (TX, TXBAR , TXEN, CHEN) Bus terminal current (XF1, XF3) Receiver output current (RX, CD) Bus pins (XF1, XF3) All other pins All pins 16 4 1500 200 170 below regarding thermal shutdown) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DGND and CGND should be connected to a common ground plane external to the device. All voltage values, except differential I/O bus voltages, are with respect to the ground plane VCC and VDD lower limits are DC conditions, see application information regarding start-up transients. Tested in accordance JEDEC Standard 22, Test Method A114-A. Tested in accordance JEDEC Standard 22, Test Method C101. Tested in accordance JEDEC Standard 22, Test Method A115-A. If the internal junction temperature exceeds 170°C, a thermal shutdown function will disable the transmitter. DISSIPATION RATINGS CIRCUIT BOARD MODEL (1) Low-K High-K (1) (2) TA≤ 25°C 625 mW 1180 mW DERATING FACTOR (2) ABOVE TA = 25°C 5 mW/°C 9.5 mW/°C TA = 65°C 425 mW 800 mW TA = 100°C 250 mW 475 mW Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages. For additional information about JEDEC thermal models, see Texas Instruments Application Note Thermal Characteristics of Logic and Linear Packages using JEDEC PCB Designs (SZZA017). This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. 2 Submit Documentation Feedback www.ti.com SN65HVD61 SLLS770A – JANUARY 2007 – REVISED FEBRUARY 2007 RECOMMENDED OPERATING CONDITIONS MIN VCC VDD VIH VIL Analog supply voltage (1) 4.75 2.375 TX, TXBAR, TXEN, CHEN (VXF1 + VXF3 ) / 2 0.7×VDD 0 4.75 –10 130 –8 8 –1 –40 10 95% 1 100 150 Input/Output supply voltage (2) High-level logic input voltage Low-level logic input voltage Bus pin common-mode voltage NOM 5 MAX 5.25 5.25 VDD 0.3×VDD 5.25 15 150 V V mA mA mA °C Mbps UNIT V V V Voltage at any bus terminal (XF1, XF3) Transmitter peak output current (XF1, XF3) IOH IOL TA TJ High-level logic output current Low-level logic output current Output current Operating free-air temperature Junction temperature Signaling rate Relative humidity (non-condensing) (1) (2) RX, CD SIG A power-shutdown feature keeps the device disabled when the voltage at VCC is below 2.1 V. The I/O ring voltage for this device (VDD) should be the same as the power supply voltage for the controller with which it interfaces. In the case where the voltages are different, designers must consider the logic threshold compatibility between devices. Submit Documentation Feedback 3 SN65HVD61 SLLS770A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER BUS PINS (XF1, XF3) VOL(TX) VOH(TX) VO(OFF) VSW(PP) VTH+ VTHVhys VCD Transmitter output low voltage Connect to VCC through 37.5 Ω, ±1% resistor Transmitter output high voltage Transmitter off noise level, |XF3-XF1| Receiver-to-bus reflection, peak-to-peak Positive-going differential input threshold voltage Negative-going differential input threshold voltage Hysteresis voltage (VTH+– VTH-) Carrier detect threshold voltage, (XF3–XF1) T > 0°C T ≥ 40°C T ≥– 40°C VCC–0.1 VCC 5 200 35 –120 50 23 –35 70 175 255 1.2 –1.7 –1.7 –400 12 7 11 1.2 400 mA 120 mV mV mV mV mV mV 0.9 1.25 1.35 V TEST CONDITIONS MIN TYP (1) MAX UNIT RL = 37.5 Ω, 0 to 20 MHz BW, TX and TXBAR inputs idle, CHEN and TXEN inputs LO R1=R2=50 Ω, C1=C2=15pF, See Figure 3 4.75V < Vcm < 5.25 4.75V < Vcm < 5.25 4.75V < Vcm < 5.25, RX output 4.75V < Vcm < 5.25 VI = 10V, TXEN at 0V, Other input at –10V to 10 V VI = –10V, TXEN at 0V Other input at –10V to 10 V VCC < 2V, VI = -10V to 10V Other input at –10 V to 10 V 0 < VO < VCC VI = –10V to 10V, Other input at CGND, DC 10 MHz AC test frequency, 1Vp-p amplitude using HP4194A or equivalent impedance analyzer, VCC = 0V TX, TXBAR, TXEN, CHEN VDD at 0 V, TX,TXBAR, TXEN, CHEN CL = 15 pF IO = –4 mA, VDD > 3V CL = 15 pF IO = 4 mA RX, CD, 0 < VO < VDD VDD at 0 V, 0 < VO < 5.25V –20 –1 0.8×VDD 2.4 –100 –100 II Bus terminal input leakage current II(off) IOS RIN CIN Bus terminal input leakage current Short-circuit output current Bus terminal input resistance Differential input capacitance (XF1-to-XF3) mA mA kΩ pF LOGIC INPUTS (TX, TXBAR, TXEN,CHEN) II II(off) Logic input current Logic input power-off current 100 100 µA µA LOGIC OUTPUTS (RX, CD) VOH VOL IOZ IO(off) VSIG(0) GAINSIG Logic output voltage, high level V 0.2×VDD 0.4 20 1 Logic output voltage, low level Logic output high-impedance-state current Logic output power-off current V µA mA SIGNAL STRENGTH PIN (SIG) SIG output voltage with zero differential input RL = 5 kΩ voltage SIG gain ∆VO/∆VID VID switching at 10 Mbps, 20 MHz bandwidth, See Figure 10 1.125 70 1.25 100 1.375 130 V mV/V POWER SUPPLY PINS (VCC, CGND, VDD, DGND) Analog supply current (dynamic) ICC Analog supply current, chip disabled Analog supply current, Lowest power conditions IDD I/O supply current, I/O, dynamic I/O supply current, I/O, chip disabled CHEN and TXEN at logic high, No load CHEN at logic low CHEN at DGND, TX and TXBAR at VDD CHEN at logic high, no load CHEN at logic low 36 1.8 0.8 65 3 2 5 10 mA µA mA (1) All typical values are at 25°C and with a 5 V supply. For typical values with a 3.3V supply, refer to the TYPICAL CHARACTERISTICS curves. 4 Submit Documentation Feedback www.ti.com SN65HVD61 SLLS770A – JANUARY 2007 – REVISED FEBRUARY 2007 SWITCHING CHARACTERISTICS over operating recommended operating conditions (unless otherwise noted) PARAMETER TRANSMITTER tr tf tPLH tPHL tsk(p) tOUT SKEW TEST CONDITIONS MIN TYP MAX UNIT Output rise time (10%-to-90%) differential Output fall time (90%-to-10%) differential Propagation delay time, low-to-high-level differential output Propagation delay time, high-to-low-level differential output Pulse skew, differential (XF3-XF1) | tPLH – tPHL| Output delay skew, tpON – tpOFF, single-ended outputs RL = 37.5 Ω, CL = 15 pF, CHEN and TXEN at logic high, See Figure 2 0 0 RL = 37.5 Ω, CL = 15 pF, CHEN and TXEN at logic high, See Figure 1 (1) 20 20 22 24 2 7 9 30 30 50 50 5 12 12 250 400 400 400 1 V/ns ns ns ns ns tON-tOFF Symmetry, turn-on-time-to-turn-off-time, 10%/90%, each single-ended output tPZL tPLZ tPZL tPLZ SR Propagation delay time, disabled-to-low-level output Propagation delay time, low-level-to-disabled-output Propagation delay time, disabled-to-low-level output Propagation delay time, low-level-t