EMBEDDED TEST-BUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES

SN54LVT8980, SN74LVT8980 EMBEDDED TEST-BUS CONTROLLERS IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES SCBS676C – DECEMBER 1996 – REVISED AUGUST 1997 D D D D D D D D D D D D D Members of Texas Instruments (TI) Broad Family of Testability Products Supporting IEEE Std 1149.1-1990 (JTAG) Test Access Port (TAP) and Boundary-Scan Architecture Provide Built-In Access to IEEE Std 1149.1 Scan-Accessible Test/Maintenance Facilities at Board and System Levels While Powered at 3.3 V, the TAP Interface is Fully 5-V Tolerant for Mastering Both 5-V and/or 3.3-V IEEE Std 1149.1 Targets Simple Interface to Low-Cost 3.3-V Microprocessors/Microcontrollers Via 8-Bit Asynchronous Read/Write Data Bus Easy Programming Via Scan-Level Command Set and Smart TAP Control Transparently Generate Protocols to Support Multidrop TAP Configurations Using TI’s Addressable Scan Port Flexible TCK Generator Provides Programmable Division, Gated-TCK, and Free-Running-TCK Modes Discrete TAP Control Mode Supports Arbitrary TMS/TDI Sequences for Non-Compliant Targets Programmable 32-Bit Test Cycle Counter Allows Virtually Unlimited Scan/Test Length Accommodate Target Retiming (Pipeline) Delays of Up to 15 TCK Cycles Test Output Enable (TOE) Allows for External Control of TAP Signals High-Drive Outputs (–32-mA IOH, 64-mA IOL) at TAP Support Backplane Interface and/or High Fanout Package Options Include Plastic Small-Outline (DW) Package, Ceramic Chip Carriers (FK), and Ceramic 300-mil DIPs (JT) SN54LVT8980 . . . JT PACKAGE SN74LVT8980 . . . DW PACKAGE (TOP VIEW) STRB R/W D0 D1 D2 D3 GND D4 D5 D6 D7 CLKIN 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 A0 A1 A2 RDY TDO VCC TCK TMS TRST TDI RST TOE SN54LVT8980 . . . FK PACKAGE (TOP VIEW) D1 D2 D3 NC GND D4 D5 D0 R/W STRB NC A0 A1 A2 5 6 7 8 9 10 432 1 28 27 26 25 24 23 22 21 20 19 11 12 13 14 15 16 17 18 RDY TDO VCC NC TCK TMS TRST NC – No internal connection description The ’LVT8980 embedded test-bus controllers (eTBC) are members of the TI broad family of testability integrated circuits. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit assemblies. Unlike most other devices of this family, the eTBC is not a boundary-scannable device; rather, its function is to master an IEEE Std 1149.1 (JTAG) test access port (TAP) under the command of an embedded host microprocessor/microcontroller. Thus, the eTBC enables the practical and effective use of the IEEE Std 1149.1 test-access infrastructure to support embedded/built-in test, emulation, and configuration/maintenance facilities at board and system levels. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D6 D7 CLKIN NC TOE RST TDI Copyright © 1997, Texas Instruments Incorporated 1 SN54LVT8980, SN74LVT8980 EMBEDDED TEST-BUS CONTROLLERS IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES SCBS676C – DECEMBER 1996 – REVISED AUGUST 1997 description (continued) The eTBC masters all TAP signals required to support one 4- or 5-wire IEEE Std 1149.1 serial test bus – test clock (TCK), test mode select (TMS), test data input (TDI), test data output (TDO), and test reset (TRST). All such signals can be connected directly to the associated target IEEE Std 1149.1 devices without need for additional logic or buffering. However, as well as being directly connected, the TMS, TDI, and TDO signals can be connected to distant target IEEE Std 1149.1 devices via a pipeline, with a retiming delay of up to 15 TCK cycles; the eTBC automatically handles all associated serial-data justification. Conceptually, the eTBC operates as a simple 8-bit memory- or I/O- mapped peripheral to a microprocessor/microcontroller (host). High-level commands and parallel data are passed to/from the eTBC via its generic host interface, which includes an 8-bit data bus (D7–D0) and a 3-bit address bus (A2–A0). Read/write select (R/W) and strobe (STRB) signals are implemented so that the critical host-interface timing is independent of the CLKIN period. An asynchronous ready (RDY) indicator is provided to hold off, or insert wait states into, a host read/write cycle when the eTBC cannot respond immediately to the requested read/write operation. High-level commands are issued by the host to cause the eTBC to generate the TMS sequences necessary to move the test bus from any stable TAP-controller state to any other such stable state, to scan instruction or data through test registers in target devices, and/or to execute instructions in the Run-Test/Idle TAP state. A 32-bit counter can be programmed to allow a predetermined number of scan or execute cycles. During scan operations, serial data that appears at the TDI input is transferred into a serial-to-4 × 8-bit-parallel first-in/first-out (FIFO) read buffer, which can then be read by the host to obtain the return serial-data stream up to eight bits at a time. Serial data that is to be transmitted from the TDO output is written by the host, up to eight bits at a time, to a 4 × 8-bit-parallel-to-serial FIFO write buffer. In addition to such simple state-movement, scan, and run-test operations, the eTBC supports several additional commands that provide for input-only scans, output-only scans, recirculate scans (in which TDI is mirrored back to TDO), and a scan mode that generates the protocols used to support multidrop TAP configurations using TI’s addressable scan port. Two loopback modes also are supported that allow the microprocessor/microcontroller host to monitor the TDO or TMS data streams output by the eTBC. The eTBC’s flexible clocking architecture allows the user to choose between free-running (in which the TCK always follows CLKIN) and gated modes (in which the TCK output is held static except during state-move, run-test, or scan cycles) as well as to divide down TCK from CLKIN. A discrete mode is also available in which the TAP is driven strictly by read/write cycles under full control of the microprocessor/microcontroller host. These features ensure that virtually any IEEE Std 1149.1 target device or device chain – even where such may not fully comply to IEEE Std 1149.1 – can be serviced by the eTBC. While most operations of the eTBC are synchronous to CLKIN, a test-output enable (TOE) is provided for output control of the TAP outputs, and a reset (RST) input is provided for hardware reset of the eTBC. The former can be used to disable the eTBC so that an external controller can master the associated IEEE Std 1149.1 test bus. The SN54LVT8980 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74LVT8980 is characterized for operation from –40°C to 85°C. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LVT8980, SN74LVT8980 EMBEDDED TEST-BUS CONTROLLERS IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES SCBS676C – DECEMBER 1996 – REVISED AUGUST 1997 functional block diagram VCC 14 VCC VCC 15 STRB 1 TDI Buffer TDI 21 RST RDY R/W 2 Host Interface Command/ Control TDO Buffer 20 TDO A2–A0 22–24 TAP-State Generator 11–8, 6–3 17 TMS D7–D0 18 TCK Discrete Control 16 12 CLKIN VCC 13 TCK Generator TRST TOE Pin numbers shown are for the DW and JT packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LVT8980, SN74LVT8980 EMBEDDED TEST-BUS CONTROLLERS IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES SCBS676C – DECEMBER 1996 – REVISED AUGUST 1997 Terminal Functions TERMINAL NAME A2–A0 CLKIN DESCRIPTION Address inputs. A2–A0 form the 3-bit address bus that interfaces the eTBC to its microprocessor/microcontroller host. These inputs directly index the eTBC register to be accessed (read from or written to). Clock input. CLKIN is the system clock input for the eTBC. Most operations of the eTBC are synchronous to CLKIN. Internally, the CLKIN signal is divided by a programmable divisor to generate TCK. Data inputs/outputs. D7–D0 form the 8-bit bidirectional data bus that interfaces the eTBC to its microprocessor/microcontroller host. Data in the eTBC registers is accessed (read or written) using this data bus. D7 is considered the most-significant bit, while D0 is considered the least-significant bit. Ground Ready output. RDY is used to indicate to the microprocessor/microcontroller host whether or not the eTBC is ready to service the access (read or write) operation that is currently being requested. If RDY remains high following the initiation of an access cycle (STRB negative edge) then the eTBC is ready. Otherwise, if RDY goes low following the initiation of an access cycle (STRB negative edge) then the eTBC is not ready. In cases where the eTBC is not ready, subsequent processing in the eTBC may clear the not-ready state, which allows RDY to return high before the end of the access cycle. In any event, the RDY output returns high upon the termination of any access cycle (STRB positive edge). Reset input. RST is used to initiate asynchronous reset of the eTBC. Assertion (low) of RST places the eTBC in a reset state from which it does not exit until RST is released (high). While RST is low, the eTBC ignores host writes, the RDY, TDO, TMS, and TRST outputs are high, while TCK outputs CLKIN/16. An internal pullup forces RST to a high level if it has no external connection. Read/write select. R/W is used by the microprocessor/microcontroller host to instruct the eTBC