12-BIT ASYNCHRONOUS BINARY COUNTERS

SN54LV4040A, SN74LV4040A 12-BIT ASYNCHRONOUS BINARY COUNTERS SCES226A – APRIL 1999 – REVISED SEPTEMBER 1999 D D D D D D D D D D EPIC™ (Enhanced-Performance Implanted CMOS) Process Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C High On-Off Output-Voltage Ratio Low Crosstalk Between Switches Individual Switch Controls Extremely Low Input Current Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) Package Options Include Plastic Small-Outline (D, NS), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Ceramic (J) DIPs SN54LV4040A . . . J OR W PACKAGE SN74LV4040A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) QL QF QE QG QD QC QB GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC QK QJ QH QI CLR CLK QA SN54LV4040A . . . FK PACKAGE (TOP VIEW) QE QG NC QD QC 4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13 NC VCC QK QJ QH NC QI CLR description The ’LV4040A devices are 12-bit asynchronous binary counters with the outputs of all stages available externally. A high level at the clear (CLR) input asynchronously clears the counter and resets all outputs low. The count is advanced on a high-to-low transition at the clock (CLK) input. Applications include time-delay circuits, counter controls, and frequency-dividing circuits. NC – No internal connection The SN54LV4040A is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74LV4040A is characterized for operation from –40°C to 85°C. FUNCTION TABLE (each buffer) INPUTS CLK ↑ ↓ X CLR L L H FUNCTION No change Advance to next stage All outputs L Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 Copyright © 1999, Texas Instruments Incorporated • DALLAS, TEXAS 75265 QB GND NC QA CLK QF QL 1 SN54LV4040A, SN74LV4040A 12-BIT ASYNCHRONOUS BINARY COUNTERS SCES226A – APRIL 1999 – REVISED SEPTEMBER 1999 logic symbol† RCTR12 0 9 7 6 5 CLR 11 CT=0 CT 3 2 CLK 10 4 13 12 14 15 11 1 QA QB QC QD QE QF QG QH QI QJ QK QL † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages. logic diagram (positive logic) CLR 11 R CLK 10 T R T R T R T R T 9 QA 7 QB 6 QC 5 QD 3 QE R T R T R T R T R T R T R T 2 QF 4 QG 13 QH 12 QI 14 QJ 15 QK 1 QL Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LV4040A, SN74LV4040A 12-BIT ASYNCHRONOUS BINARY COUNTERS SCES226A – APRIL 1999 – REVISED SEPTEMBER 1999 absolute maximum ratings over operating free-air temperature range† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 7 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 4) SN54LV4040A MIN VCC Supply voltage VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 0 0 VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 0 0 0 2 1.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 0.5 VCC × 0.3 VCC × 0.3 VCC × 0.3 5.5 VCC –50 –2 –6 –12 50 2 6 12 200 100 20 0 0 0 0 0 MAX 5.5 SN74LV4040A MIN 2 1.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 0.5 VCC × 0.3 VCC × 0.3 VCC × 0.3 5.5 VCC –50 –2 –6 –12 50 2 6 12 200 100 20 ns/V mA µA mA V V MAX 5.5 UNIT V VIH High-level High level input voltage VIL Low-level Low level input voltage VI VO Input voltage Output voltage V V µA IOH High-level High level output current IOL Low-level Low level output current ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature –55 125 –40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LV4040A, SN74LV4040A 12-BIT ASYNCHRONOUS BINARY COUNTERS SCES226A – APRIL 1999 – REVISED SEPTEMBER 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –50 µA IOH = –2 mA IOH = –6 mA IOH = –12 mA IOL = 50 µA IOL = 2 mA IOL = 6 mA IOL = 12 mA VI = VCC or GND VI = VCC or GND, VI or VO = 0 to 5.5 V VI = VCC or GND IO = 0 SN54LV4040A VCC 2 V to 5.5 V 2.3 V 3V 4.5 V 2 V to 5.5 V 2.3 V 3V 4.5 V 5.5 V 5.5 V 0V 3.3 V 5V 1.9 1.8 MIN VCC–0.1 2 2.48 3.8 0.1 0.4 0.44 0.55 ±1 20 5 1.9 1.8 TYP MAX SN74LV4040A MIN VCC–0.1 2 2.48 3.8 0.1 0.4 0.44 0.55 ±1 20 5 µA µA µA pF V TYP MAX UNIT VOH V VOL II ICC Ioff Ci timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw tsu Pulse duration Setup time CLK high or low CLR high CLR inactive before CLK↓ 7 6.5 6.5 SN54LV4040A MIN 7 6.5 6.5 MAX SN74LV4040A MIN 7 6.5 6.5 MAX UNIT ns ns timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw tsu Pulse duration Setup time CLK high or low CLR high CLR inactive before CLK↓ 5 5 5 SN54LV4040A MIN 5 5 5 MAX SN74LV4040A MIN 5 5 5 MAX UNIT ns ns timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw tsu Pulse duration Setup time CLK high or low CLR high CLR inactive before CLK↓ 5 5 5 SN54LV4040A MIN 5 5 5 MAX SN74LV4040A MIN 5 5 5 MAX UNIT ns ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LV4040A, SN74LV4040A 12-BIT ASYNCHRONOUS BINARY COUNTERS SCES226A – APRIL 1999 – REVISED SEPTEMBER 1999 switching characteristics over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH* tPHL* tPHL* tPLH tPHL tPHL ∆tpd CLK CLR CLK CLR Qn QA Any Q QA Any Q Qn+1 FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE CL = 15 pF* CL = 50 pF CL = 15 pF CL = 15 pF CL = 50 pF CL = 50 pF CL = 50 pF MIN 50 40 TA = 25°C TYP MAX 115 95 8.7 8.7 9.3 10.5 10.5 11.7 1.7 19.4 19.4 19.9 24.1 24.1 24.5 5.9 SN54LV4040A MIN 40 35 1 1 1 1 1 1 23 23 24 28 28 28 7 MAX SN74LV4040A MIN 40 35