SN54LV393A, SN74LV393A DUAL 4-BIT BINARY COUNTERS
SCLS457B – FEBRUARY 2001 – REVISED JULY 2003
D D D D D D D D D D
2-V to 5.5-V VCC Operation Max tpd of 10 ns at 5 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C Ioff Supports Partial-Power-Down-Mode Operation Dual 4-Bit Binary Counters With Individual Clocks Direct Clear for Each 4-Bit Counter Can Significantly Improve System Densities by Reducing Counter Package Count by 50 Percent Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101)
SN54LV393A . . . J OR W PACKAGE SN74LV393A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW)
1CLK 1CLR 1QA 1QB 1QC 1QD GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC 2CLK 2CLR 2QA 2QB 2QC 2QD
SN54LV393A . . . FK PACKAGE (TOP VIEW)
1CLR 1CLK NC VCC 2CLK 1QA NC 1QB NC 1QC
3 4 5 6 7 8 2 1 20 19 18 17 16 15 14 9 10 11 12 13
description/ordering information
The ’LV393A devices contain eight flip-flops and additional gating to implement two individual 4-bit counters in a single package. These devices are designed for 2-V to 5.5-V VCC operation. ORDERING INFORMATION
TA SOIC – D SOP – NS –40°C to 85°C 40°C SSOP – DB TSSOP – PW TVSOP – DGV CDIP – J –55°C to 125°C CFP – W LCCC – FK PACKAGE† Tube of 50 Reel of 2500 Reel of 2000 Reel of 2000 Tube of 90 Reel of 2000 Reel of 250 Reel of 2000 Tube of 25 Tube of 150 Tube of 55
2CLR NC 2QA NC 2QB
NC – No internal connection
ORDERABLE PART NUMBER SN74LV393AD SN74LV393ADR SN74LV393ANSR SN74LV393ADBR SN74LV393APW SN74LV393APWR SN74LV393APWT SN74LV393ADGVR SNJ54LV393AJ SNJ54LV393AW SNJ54LV393AFK
SNJ54LV393AFK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1QD GND NC 2QD 2QC
TOP-SIDE MARKING LV393A 74LV393A LV393A LV393A LV393A SNJ54LV393AJ SNJ54LV393AW
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SN54LV393A, SN74LV393A DUAL 4-BIT BINARY COUNTERS
SCLS457B – FEBRUARY 2001 – REVISED JULY 2003
description/ordering informaton (continued)
These devices comprise two independent 4-bit binary counters, each having a clear (CLR) and a clock (CLK) input. These devices change state on the negative-going transition of the CLK pulse. N-bit binary counters can be implemented with each package, providing the capability of divide by 256. The ’LV393A devices have parallel outputs from each counter stage so that any submultiple of the input count frequency is available for system timing signals. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE INPUTS CLK ↑ ↓ X CLR L L H FUNCTION No change Advance to next stage All outputs L
logic diagram, each counter (positive logic)
CLR CLK R Q T QA
R Q T QB
R Q T QC
R Q T QD
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POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LV393A, SN74LV393A DUAL 4-BIT BINARY COUNTERS
SCLS457B – FEBRUARY 2001 – REVISED JULY 2003
timing diagram
CLK CLR
QA QB Outputs QC QD Count Up Clear
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Output voltage range applied in high or low state, VO (see Notes 1 and 2) . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range applied in power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 7 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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SN54LV393A, SN74LV393A DUAL 4-BIT BINARY COUNTERS
SCLS457B – FEBRUARY 2001 – REVISED JULY 2003
recommended operating conditions (see Note 4)
SN54LV393A MIN VCC Supply voltage VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 0 0 VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 2 1.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 0.5 VCC × 0.3 VCC × 0.3 VCC × 0.3 5.5 VCC –50 –2 –6 –12 50 2 6 12 200 100 20 0 0 MAX 5.5 SN74LV393A MIN 2 1.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 0.5 VCC × 0.3 VCC × 0.3 VCC × 0.3 5.5 VCC –50 –2 –6 –12 50 2 6 12 200 100 20 ns/V mA µA mA V V MAX 5.5 UNIT V
VIH
High-level High level input voltage
VIL
Low-level Low level input voltage
VI VO
Input voltage Output voltage
V V µA
IOH
High-level High level output current
IOL
Low-level Low level output current
∆t/∆v
Input transition rise or fall rate
TA Operating free-air temperature –55 125 –40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS IOH = –50 µA IOH = –2 mA IOH = –6 mA IOH = –12 mA IOL = 50 µA IOL = 2 mA IOL = 6 mA IOL = 12 mA VI = 5.5 V or GND VI = VCC or GND, VI or VO = 0 to 5.5 V VI = VCC or GND IO = 0 SN54LV393A VCC 2 V to 5.5 V 2.3 V 3V 4.5 V 2 V to 5.5 V 2.3 V 3V 4.5 V 0 to 5.5 V 5.5 V 0 3.3 V 1.8 MIN VCC–0.1 2 2.48 3.8 0.1 0.4 0.44 0.55 ±1 20 5 1.8 TYP MAX SN74LV393A MIN VCC–0.1 2 2.48 3.8 0.1 0.4 0.44 0.55 ±1 20 5 µA µA µA pF V TYP MAX UNIT
VOH
V
VOL
II ICC Ioff Ci
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LV393A, SN74LV393A DUAL 4-BIT BINARY COUNTERS
SCLS457B – FEBRUARY 2001 – REVISED JULY 2003
timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
TA = 25°C MIN MAX tw tsu Pulse duration Setup time CLK high or low CLR high CLR inactive before CLK↓ 5 5 6 SN54LV393A MIN 5 5 6 MAX SN74LV393A MIN 5 5 6 MAX UNIT ns ns
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
TA = 25°C MIN MAX tw tsu Pulse duration Setup time CLK high or low CLR high CLR inactive before CLK↓ 5 5 5 SN54LV393A MIN 5 5 5 MAX SN74LV393A MIN 5 5 5 MAX UNIT ns ns
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C MIN MAX tw tsu Pulse duration Setup time CLK high or low CLR high CLR inactive before CLK↓ 5 5 4 SN54LV393A MIN 5 5 4 MAX SN74LV393A MIN 5 5 4 MAX UNIT ns ns
switching characteristics over recommended operating VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER fmax QA tpd d CLK QB QC QD tPHL CLR Qn QA tpd d CLK QB QC QD tPHL CLR Qn * On products compliant to MIL-PRF-38535, this pa
