DIGITAL SIGNAL PROCESSORS

SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS SGUS026B– APRIL 1998 – REVISED APRIL 1999 D D D D D D D D D D D D D – 55°C to 125°C Operating Temperature Range, QML Processing Processed to MIL-PRF-38535 (QML) SMD Approval for 40- and 50-MHz Versions High-Performance Floating-Point Digital Signal Processor (DSP): – SMJ320C31-50 (5 V) 40-ns Instruction Cycle Time 275 Million Operations Per Second (MOPS), 50 Million Floating-Point Operations Per Second (MFLOPS), 25 Million Instructions Per Second (MIPS) – SMJ320C31-40 (5 V) 50-ns Instruction Cycle Time 220 MOPS, 40 MFLOPS, 20 MIPS – SMJ320LC31-40 (3.3 V) 50-ns Instruction Cycle Time 220 MOPS, 40 MFLOPS, 20 MIPS – SMQ320LC31-40 (3.3 V) 50-ns Instruction Cycle Time 220 MOPS, 40 MFLOPS, 20 MIPS 32-Bit High-Performance CPU 16- / 32-Bit Integer and 32- / 40-Bit Floating-Point Operations 32-Bit Instruction and Data Words, 24-Bit Addresses Two 1K Word × 32-Bit Single-Cycle Dual-Access On-Chip RAM Blocks Boot-Program Loader 64-Word × 32-Bit Instruction Cache Eight Extended-Precision Registers Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs) Two Low-Power Modes D D D D D D D D D D D D D D D On-Chip Memory-Mapped Peripherals: – One Serial Port Supporting 8- / 16- / 24- / 32-Bit Transfers – Two 32-Bit Timers – One-Channel Direct Memory Access (DMA) Coprocessor for Concurrent I/O and CPU Operation Fabricated Using 0.7 µm Enhanced Performance Implanted CMOS (EPIC™) Technology by Texas Instruments (TI™) Two- and Three-Operand Instructions 40 / 32-Bit Floating-Point / Integer Multiplier and Arithmetic Logic Unit (ALU) Parallel ALU and Multiplier Execution in a Single Cycle Block-Repeat Capability Zero-Overhead Loops With Single-Cycle Branches Conditional Calls and Returns Interlocked Instructions for Multiprocessing Support Bus-Control Registers Configure Strobe-Control Wait-State Generation Validated Ada Compiler Integer, Floating-Point, and Logical Operations 32-Bit Barrel Shifter One 32-Bit Data Bus (24-Bit Address) Packaging – 132-Lead Ceramic Quad Flatpack With Nonconductive Tie-Bar (HFG Suffix) – 141-Pin Ceramic Staggered Pin Grid- Array Package (GFA Suffix) – 132-Lead TAB Frame – 132-Lead Plastic Quad Flatpack (PQ Suffix) description The SMJ320C31, SMJ320LC31, and SMQ320LC31 digital signal processors (DSPs) are 32-bit, floating-point processors manufactured in 0.72-µm triple-level-metal CMOS technology. The devices are part of the SMJ320C3x generation of DSPs from Texas Instruments. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and TI are trademarks of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999, Texas Instruments Incorporated On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS SGUS026B– APRIL 1998 – REVISED APRIL 1999 description (continued) The SMJ320C3x internal busing and special digital-signal-processing instruction set have the speed and flexibility to execute up to 50 MFLOPS. The SMJ320C3x optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip. The SMJ320C3x can perform parallel multiply and ALU operations on integer or floating-point data in a single cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs, internal dual-access memories, one DMA channel supporting concurrent I/O, and a short machine-cycle time. High performance and ease of use are results of these features. General-purpose applications are greatly enhanced by the large address space, multiprocessor interface, internally and externally generated wait states, one external interface port, two timers, one serial port, and multiple-interrupt structure. The SMJ320C3x supports a wide variety of system applications from host processor to dedicated coprocessor. High-level-language support is easily implemented through a register-based architecture, large address space, powerful addressing modes, flexible instruction set, and well-supported floating-point arithmetic. 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS SGUS026B– APRIL 1998 – REVISED APRIL 1999 141-PIN GFA STAGGERED GRID ARRAY PACKAGE ( BOTTOM VIEW ) TA PACKAGE ( TOP VIEW ) 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 Die Face Up 132 1 100 99 Tab Leads Up B A C D FHKM P T V EGJLN RUW 33 34 66 67 132-PIN HFG QUAD FLATPACK ( TOP VIEW ) TB PACKAGE ( TOP VIEW ) 1 ÉÉ ÉÉÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ 33 34 66 ÉÉ ÉÉ ÉÉ ÉÉ 100 99 67 POST OFFICE BOX 1443 ÉÉ ÉÉÉÉ ÉÉ 132 132 1 Tab Leads Up 100 99 Die Face Up 33 34 66 67 • HOUSTON, TEXAS 77251–1443 3 SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS SGUS026B– APRIL 1998 – REVISED APRIL 1999 SMQ320LC31 pinout (top view) The SMQ320LC31 device is also packaged in a132-pin plastic quad flatpack (PQ Suffix). The full part numbers are SMQ320LC31PQM40 and 5962-9760601NXB. PQ PACKAGE (TOP VIEW) MCBL/MP EMU2 EMU1 EMU0 EMU3 TCLK1 VDD TCLK0 VSS VSS A10 VDD A11 A12 A13 A14 A15 A16 A17 A18 VDD A20 A21 VDD VDD 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 SHZ VSS A19 VSS VSS A22 A23 VSS A9 VSS A8 A7 A6 A5 VDD A4 A3 A2 A1 A0 VSS D31 VDD VDD D30 VSS VSS VSS D29 D28 VDD D27 VSS D26 D25 D24 D23 D22 D21 VDD D20 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 DX0 VDD FSX0 VSS CLKX0 CLKR0 FSR0 VSS DR0 INT3 INT2 VDD VDD INT1 VSS VSS INT0 IACK XF1 VDD XF0 RESET R/W STRB RDY VDD HOLD HOLDA X1 X2/CLKIN VSS VSS VSS D19 D18 D17 D16 D15 V SS D14 V DD D13 V SS D12 D11 D10 V DD V DD D9 D8 VSS VSS VSS D7 D6 V SS V DD D5 D4 D3 D2 D1 D0 H1 H3 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 V DD SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS SGUS026B– APRIL 1998 – REVISED APRIL 1999 Terminal Assignments PIN NUMBER PQ PKG 29 28 27 26 25 23 22 21 20 18 16 14 13 12 11 10 9 8 7 5 2 1 130 129 111 112 80 79 78 77 76 75 73 72 68 HFG PKG 12 11 10 9 8 6 5 4 3 1 131 129 128 127 126 125 124 123 122 120 117 116 113 112 94 95 63 62 61 60 59 58 56 55 51 GFA PKG L1 K2 J1 J3 G1 F2 E1 E3 D2 C1 C3 B2 A1 C5 B4 A3 C7 B6 C9 B8 A7 A9 B10 A11 E17 A19 W19 V16 W17 U13 V14 W15 U11 V12 W11 NAME A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 CLKR0 CLKX0 D0 D1 D2 D3 D4 D5 D6 D7 D8 PQ PKG 64 63 62 60 58 56 55 54 53 52 50 48 47 46 45 44 43 41 39 38 34 31 108 116 124 125 126 123 110 114 81 82 90 89 99 100 NUMBER HFG PKG 47 46 45 43 41 39 38 37 36 35 33 31 30 29 28 27 26 24 22 21 17 14 91 99 107 108 109 106 93 97 73 72 64 65 82 83 GFA PKG W9 U9 V8 W7 U7 V6 W5 U5 V4 W3 U3 V2 W1 R3 T2 U1 N3 P2 R1 L3 M2 N1 C19 C17 B14 A13 B12 A15 D18 B18 P18 R19 V18 U17 H18 J17 NAME D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 DR0 DX0 EMU0 EMU1 EMU2 EMU3 FSR0 FSX0 HOLD HOLDA H1 H3 IACK INT0 PIN 67 50 V10 D9 † CVSS, VSSL, and IVSS are on the same plane. ‡ AVDD, DVDD, CVDD, and PVDD are on the same plane. § VSUBS connects to die metallization. Tie this pin to clean ground. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 5 SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS SGUS026B– APRIL 1998 – REVISED APRIL 1999 Terminal Assignments (Continued) PIN NUMBER PQ PKG 103 106 107 127 92 95 94 118 93 120 HFG PKG 86 89 90 110 77 75 78 101 76 103 105 121 6 15 24 32 33 40 49 59 65 66 74 83 91 97 104 105 115 121 131 132 3 4 17 130 7 15 16 23 32 42 48 49 57 66 74 80 87 88 98 104 114 115 118 119 132 2 GFA PKG E19 F18 G17 C11 L19 N17 K18 A17 M19 B16 C15 G5 E7 E5 N5 R5 H4 J5 T14 R7 R9 R13 R15 P16 N15 G15 E15 L15 E9 E13 E11 L5 H2 M4 F4 NAME INT1 INT2 INT3 MCBL/MP R/W RDY RESET SHZ STRB TCLK0 TCLK1 AVDD‡ AVDD‡ AVDD‡ VDDL VDDL DVDD‡ DVDD‡ DVDD‡ VDDL VDDL DVDD‡ DVDD‡ CVDD‡ CVDD‡ VDDL VDDL PVDD‡ PVDD‡ VDDL VDDL VSSL† DVSS CVSS† DVSS CVSS† PQ PKG 30 35 36 37 42 51 57 61 69 70 71 84 85 86 101 102 109 113 117 119 128 88 87 96 98 NUMBER HFG PKG 18 19 20 25 34 40 44 52 53 54 67 68 69 84 85 92 96 100 102 111 71 70 79 81 GFA PKG P4 T10 K4 T4 G3 K16 T8 T12 R11 J15 W13 D10 D16 T16 D12 F16 H16 D14 U15 C13 T18 U19 J19 G19 F6 D4 N19 R17 L17 M16 D6 A5 D8 NAME VSSL† VSSL† DVSS IVSS† DVSS CVSS† IVSS† DVSS VSSL† VSSL† DVSS CVSS† IVSS† DVSS VSSL† CVSS† IVSS† VSUBS§ DVSS CVSS† X1 X2/CLKIN XF0 XF1 No Connect DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS PIN 19 13 T6 † CVSS, VSSL, and IVSS are on the same plane. ‡ AVDD, DVDD, CVDD, and PVDD are on the same plane. § VSUBS connects to die metallization. Tie this pin to clean ground. 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS SGUS026B– APRIL 1998 – REVISED APRIL 1999 Terminal Functions TERMINAL NAME QTY PRIMARY-BUS INTERFACE D31 – D0 A23 – A0