DIGITAL SIGNAL PROCESSOR

SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR SGUS020 – JUNE 1996 D D D D D 1 34 D D D D D D D D D D D D D D D D GFA PACKAGE (TOP VIEW) A C E G J L N R U W B D F H K M P T V 2 1 3 4 5 6 8 10 12 14 16 18 7 9 11 13 15 17 19 PQ PACKAGE (TOP VIEW) 17 18 1 132 117 116 66 33 50 51 83 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. † IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture EPIC and TI are trademarks of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1996, Texas Instruments Incorporated POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ÉÉ ÉÉ ÉÉ ÉÉ 100 99 ÉÉ ÉÉÉÉ ÉÉ ÉÉ ÉÉÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ 132 Military Operating Temperature Range: – 55°C to 125°C Processed to MIL-PRF-38535 Fast Instruction Cycle Time (30 ns and 40 ns) Source-Code Compatible With All ’C1x and ’C2x Devices RAM-Based Operation – 9K × 16-Bit Single-Cycle On-Chip Program/Data RAM – 1056 × 16-Bit Dual-Access On-Chip Data RAM 2K × 16-Bit On-Chip Boot ROM 224K × 16-Bit Maximum Addressable External Memory Space (64K Program, 64K Data, 64K I/O, and 32K Global) 32-Bit Arithmetic Logic Unit (ALU) – 32-bit Accumulator (ACC) – 32-Bit Accumulator Buffer (ACCB) 16-Bit Parallel Logic Unit (PLU) 16 × 16-Bit Multiplier, 32-Bit Product 11 Context-Switch Registers Two Buffers for Circular Addressing Full-Duplex Synchronous Serial Port Time-Division Multiplexed Serial Port (TDM) Timer With Control and Counter Registers 16 Software Programmable Wait-State Generators Divide-by-One Clock Option IEEE 1149.1† Boundary Scan Logic Operations Are Fully Static Enhanced Performance Implanted CMOS (EPIC™) 0.72-µm Technology Fabricated by Texas Instruments Packaging – 141-Pin Ceramic Grid Array (GFA Suffix) – 132-Lead Ceramic Quad Flat Package (HFG Suffix) – 132-Lead Plastic Quad Flat Package (PQ Suffix) HFG PACKAGE (TOP VIEW) 67 84 1 SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR SGUS020 – JUNE 1996 description The SMJ320C50 digital signal processor (DSP) is a high-performance, 16-bit, fixed-point processor manufactured in 0.72-µm double-level metal CMOS technology. The SMJ320C50 is the first DSP from TI designed as a fully static device. Full-static CMOS design contributes to low power consumption while maintaining high performance, making it ideal for applications such as battery-operated communications systems, satellite systems, and advanced control algorithms. A number of enhancements to the basic SMJ320C2x architecture give the ’C50 a minimum 2× performance over the previous generation. A four-deep instruction pipeline, incorporating delayed branching, delayed call to subroutine, and delayed return from subroutine, allows the ’C50 to perform instructions in fewer cycles. The addition of a parallel logic unit (PLU) gives the ’C50 a method for manipulating bits in data memory without using the accumulator and ALU. The ’C50 has additional shifting and scaling capability for proper alignment of multiplicands or storage of values to data memory. The ’C50 achieves its low-power consumption through the IDLE2 instruction. IDLE2 removes the functional clock from the internal hardware of the ’C50, which puts it into a total-sleep mode that uses only 7 µA. A low-logic level on an external interrupt with a duration of at least five clock cycles ends the IDLE2 mode. The ’C50 is available with two clock speeds. The clock frequencies are 50 MHz, providing a 40-ns cycle time, and 66 MHz, providing a 30-ns cycle time. The available options are listed in the following table. AVAILABLE OPTIONS SUPPLY VOLTAGE TOLERANCE ±5% ±5% ±5% ±5% ±5% PART NUMBER SMJ320C50GFAM66 SMJ320C50HFGM66 SMJ320C50GFAM50 SMJ320C50HFGM50 SMQ320C50PQM66† SPEED 30-ns cycle time 30-ns cycle time 40 ns cycle time 40 ns cycle time 30 ns cycle time PACKAGE Pin grid array Quad flat package Pin grid array Quad flat package Plastic Quad flat package † When ordering use DESC P/N 5962-9455804NZD 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR SGUS020 – JUNE 1996 functional block diagram Program Bus (Address) Program Bus (Data) IPTR BMAR INT# INTM IMR IFR MUX PC(16) PASR BRAF MP/MC PAER CNF RAM Compare Stack (8 × 16) Program Memory BRCR Data Bus (Data) TRM TREG2 TREG1 TREG0 MUX Multiplier MUX MUX COUNT PREG(32) PM Prescaler P-Scaler MUX OVM SXM ALU(32) ACCB(32) ACC(32) Post-Scaler OV TC C DBMR MUX BIM PLU(16) Data Bus (Data) MUX ARP CBER INDX ARCR NDX AUXREGS (8 × 16) CBSR DP(9) dma(7) MUX CBCR ARB MUX MUX ARAU(16) Data Bus (Address) Data Memory CNF OVLY GREG BR XF POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 3 SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR SGUS020 – JUNE 1996 pin assignments PQ PKG 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 HFG PKG 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 H4 K2 U5 V4 L1 N1 M2 L3 R1 P2 N3 T2 R3 E5 E7 E3 D2 C1 G3 F2 E1 J3 H2 G1 C3 D4 J1 D12 F4 D8 D10 GFA PKG NAME NC† NC† VSS3 VSS4 NC† D7 D6 D5 D4 D3 D2 D1 D0(LSB) TMS VDD3 VDD4 TCK VSS5 VSS6 NC† INT1 INT2 INT3 INT4 NMI DR TDR FSR CLKR VDD5 VDD6 NC† NC† NC† NC† VSS7 VSS8 A0 A1 PQ PKG 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 HFG PKG 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 R17 T18 U19 N17 P18 R19 L17 P4 T4 E13 G5 V16 U15 W11 W13 V12 U11 W15 V14 U13 GFA PKG W3 U7 V6 W5 U9 V8 W7 W9 E9 E11 V10 K4 M4 NAME A2 A3 A4 A5 A6 A7 A8 A9 VDD7 VDD8 TDI VSS9 VSS10 NC† CLKMD1 A10 A11 A12 A13 A14 A15(MSB) NC† NC† VDD9 VDD10 RD WE NC† NC† VSS11 VSS12 NC† DS IS PS R/W STRB BR CLKIN2 † NC = No internal connection GFA Package additional connections: VDD: R11, E15, G15, J15, L15, N15, R13, R15, T16, U17, V18, W17, W19 VSS: T14, U1, U3, V2, W1, C17, C19, D14, D16, D18, F16, H16, K16, M16, P16 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR SGUS020 – JUNE 1996 pin assignments (continued) PQ PKG 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 HFG PKG 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 B18 A19 T10 T12 C15 E17 N5 R5 GFA PKG M18 N19 J5 L5 L19 T6 T8 K18 J19 G19 H18 J17 E19 F18 G17 NAME X2/CLKIN X1 VDD11 VDD12 TDO VSS13 VSS14 CLKMD2 FSX TFSX/TFRM DX TDX HOLDA XF CLKOUT1 NC† IACK VDD13 VDD14 NC† NC† NC† EMU0 EMU1/OFF VSS15 VSS16 TOUT PQ PKG 123 124 125 126 127 128 129 130 131 132 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 HFG PKG 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 GFA PKG B16 A17 C13 B14 A15 C11 B12 A13 R7 R9 A11 A9 B10 D6 A7 B8 C9 A5 B6 C7 A3 B4 C5 A1 B2 NAME TCLKX CLKX TFSR/TADD TCLKR RS READY HOLD BIO VDD15 VDD16 IAQ TRST VSS1 VSS2 MP/MC D15(MSB) D14 D13 D12 D11 D10 D9 D8 VDD1 VDD2 NC† NC† † NC = No internal connection GFA Package additional connections: VDD: R11, E15, G15, J15, L15, N15, R13, R15, T16, U17, V18, W17, W19 VSS: T14, U1, U3, V2, W1, C17, C19, D14, D16, D18, F16, H16, K16, M16, P16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 5 SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR SGUS020 – JUNE 1996 Terminal Functions PIN NAME A15 (MSB) A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 (LSB) D15 (MSB) D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) TYPE† DESCRIPTION ADDRESS AND DATA BUSES I/O/Z Parallel address bus. Multiplexed to address external data, program memory, or I/O. A0 – A15 are in the high-impedance state in hold mode and when OFF is active (low). These signals are used as inputs for external DMA access of the on-chip single-access RAM. They become inputs while HOLDA is active (low) if BR is driven low externally. I/O/Z Parallel data bus. Multiplexed to transfer data between the core CPU and external data, program memory, or I / O devices. D0 – D15 are in the high-impedance state when not outputting data, when RS or HOLD is asserted, or when OFF is active (low). These signals also are used in external DMA access of the on-chip single-access RAM. MEMORY CONTROL SIGNALS DS PS IS READY O/Z Data, program, and I/O space select signals. Always high unless asserted for communicating to a particular external space. DS, PS, and IS are in the high-impedance state in hold mode or when OFF is active (low). Data ready input. Indicates that an external device is prepared for the bus transaction to be completed. If the device is not ready (READY is low), the processor waits one cycle and checks READY again. READY also indicates a bus grant to an external device after a BR (bus request) signal. Read / write. R / W indicates transfer direction during communication to an external device and is normally in read mode (high) unless asserted for performing a write operation. R / W is in the high-impedance state in hold mode or when OFF is active (low). Used in external DMA access of the 9K RAM cell, this signal indicates the direction of the data bus for DMA reads (high) and writes (low) when HOLDA and IAQ are active (low). Strobe. Always high unless asserted to indicate an external bus cycle, STRB is in the high-impedance state in the hold mode or when OFF is active (low). Used in external DMA access of the on-chip singl