DIGITAL SIGNAL PROCESSOR

SMQ320C32 DIGITAL SIGNAL PROCESSOR SGUS027B – APRIL 1998 – REVISED MARCH 1999 D D D D D D D D D D D Military Operating Temperature Range – 55°C to 125°C; QML Processing High-Performance Floating-Point Digital Signal Processor (DSP) SMQ320C32-50 (5 V) – 40-ns Instruction Cycle Time – 275 MOPS – 50 MFLOPS – 25 MIPS SMQ320C32-60 (5 V) – 33-ns Instruction Cycle Time – 330 MOPS – 60 MFLOPS – 30 MIPS 32-Bit High-Performance CPU 16- / 32-Bit Integer and 32- / 40-Bit Floating-Point Operations 32-Bit Instruction Word, 24-Bit Addresses Two 256 × 32-Bit Single-Cycle, Dual-Access On-Chip RAM Blocks Flexible Boot-Program Loader On-Chip Memory-Mapped Peripherals: – One Serial Port – Two 32-Bit Timers – Two-Channel Direct Memory Access (DMA) Coprocessor With Configurable Priorities Enhanced External Memory Interface That Supports 8- / 16- / 32-Bit-Wide External RAM for Data Access and Program Execution From 16- / 32-Bit-Wide External RAM SMJ320C30 and SMJ320C31 Object Code Compatible Fabricated Using 0.7-µm Enhanced Performance Implanted CMOS (EPIC™) Technology by Texas Instruments D D D D D D D D D D D D D D D 144-Pin Plastic Quad Flatpack ( PCM Suffix ) 5 V Eight Extended-Precision Registers Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs) Two Low-Power Modes Two- and Three-Operand Instructions Parallel Arithmetic Logic Unit (ALU) and Multiplier Execution in a Single Cycle Block-Repeat Capability Zero-Overhead Loops With Single-Cycle Branches Conditional Calls and Returns Interlocked Instructions for Multiprocessing Support One External Pin, PRGW, That Configures the External-Program-Memory Width to 16 or 32 Bits Two Sets of Memory Strobes (STRB0 and STRB1) and One I / O Strobe (IOSTRB) Allow Zero-Glue Logic Interface to Two Banks of Memory and One Bank of External Peripherals Separate Bus-Control Registers for Each Strobe-Control Wait-State Generation, External Memory Width, and Data Type Size STRB0 and STRB1 Memory Strobes Handle 8-, 16-, or 32-Bit External Data Accesses (Reads and Writes) Multiprocessor Support Through the HOLD and HOLDA Signals Is Valid for All Strobes description The SMQ320C32 is a member of the ’320C3x generation of digital signal processors from Texas Instruments. The SMQ320C32 is an enhanced 32-bit floating-point processor manufactured in 0.7-µm triple-level-metal CMOS technology. The enhancements to the ’320C3x architecture include a variable-width external-memory interface, faster instruction cycle time, power-down modes, two-channel DMA coprocessor with configurable priorities, flexible bootloader, relocatable interrupt-vector table, and edge- or level-triggered interrupts. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999, Texas Instruments Incorporated On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 SMQ320C32 DIGITAL SIGNAL PROCESSOR SGUS027B – APRIL 1998 – REVISED MARCH 1999 description (continued) The internal busing and special digital signal processing instruction set of the SMQ320C32 have the speed and flexibility to execute up to 50 million floating-point operations per second (MFLOPS). The SMQ320C32 optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip. PCM PACKAGE† ( TOP VIEW ) NC INT3 INT2 INT1 INT0 IACK XF1 XF0 DV SS CVSS RESET PRGW R/W STRB1_B0 STRB1_B1 DVDD STRB1_B2 / A –2 V SSL STRB1_B3 / A–1 V DDL V DDL STRB0_B0 STRB0_B1 STRB0_B2 / A –2 STRB0_B3 / A –1 IOSTRB IVSS RDY DV DD HOLD HOLDA CLKIN DV SS CVSS V SUBS NC DR0 DVDD FSR0 CLKR0 CLKX0 FSX0 DX0 IVSS SHZ TCLK0 TCLK1 DVDD EMU3 EMU0 VDDL VDDL EMU1 EMU2 VSSL MCBL / MP CVSS DVSS A23 A22 A21 A20 A19 A18 DVDD A17 A16 A15 A14 A13 CVSS DVSS 112 111 110 109 120 119 118 117 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 116 115 114 113 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 H3 H1 D0 D1 D2 D3 DVDD D4 D5 D6 D7 D8 D9 VSSL VSSL DVSS CVSS D10 DVDD D11 IVSS D12 VDDL VDDL D13 D14 D15 D16 D17 DVDD D18 D19 D20 D21 DVSS CVSS † NC=No internal connection 2 A12 DVDD A11 A10 A9 A8 A7 A6 DV DD A5 A4 A3 VDDL VDDL A2 CVSS DV SS A1 V SSL V SSL A0 DV DD D31 D30 D29 D28 D27 D26 IVSS D25 DVDD D24 D23 D22 NC POST OFFICE BOX 1443 NC • HOUSTON, TEXAS 77251–1443 SMQ320C32 DIGITAL SIGNAL PROCESSOR SGUS027B – APRIL 1998 – REVISED MARCH 1999 Pin Assignments PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 NAME DR0 DVDD FSR0 CLKR0 CLKX0 FSX0 DX0 IVSS SHZ TCLK0 TCLK1 DVDD EMU3 EMU0 VDDL VDDL EMU1 EMU2 VSSL MCBL / MP CVSS DVSS A23 A22 A21 A20 A19 A18 DVDD NUMBER 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PIN NAME A17 A16 A15 A14 A13 CVSS DVSS NC A12 DVDD A11 A10 A9 A8 A7 A6 DVDD A5 A4 A3 VDDL VDDL A2 CVSS DVSS A1 VSSL VSSL A0 NUMBER 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 PIN NAME DVDD D31 D30 D29 D28 D27 D26 IVSS D25 DVDD D24 D23 D22 NC CVSS DVSS D21 D20 D19 D18 DVDD D17 D16 D15 D14 D13 VDDL VDDL D12 NUMBER 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 PIN NAME IVSS D11 DVDD D10 CVSS DVSS VSSL VSSL D9 D8 D7 D6 D5 D4 DVDD D3 D2 D1 D0 H1 H3 NC VSUBS CVSS DVSS CLKIN HOLDA HOLD DVDD NUMBER 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 PIN NAME RDY IVSS IOSTRB STRB0_B3 / A–1 STRB0_B2 / A–2 STRB0_B1 STRB0_B0 VDDL VDDL STRB1_B3/ A–1 VSSL STRB1_B2/ A–2 DVDD STRB1_B1 STRB1_B0 R/W PRGW RESET CVSS DVSS XF0 XF1 IACK INT0 INT1 INT2 INT3 NC POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 3 SMQ320C32 DIGITAL SIGNAL PROCESSOR SGUS027B – APRIL 1998 – REVISED MARCH 1999 pin functions This section provides signal descriptions for the SMQ320C32 device. The following table lists each signal (grouped by function), the number of pins, operating modes, and a brief signal description. Pin Functions PIN NAME NO. EXTERNAL BUS INTERFACE (70 PINS) D31 – D0 A23 – A0 R/W IOSTRB STRB0_B3 / A –1 STRB0_B2 / A –2 STRB0_B1 STRB0_B0 STRB1_B3 / A –1 STRB1_B2 / A –2 STRB1_B1 STRB1_B0 RDY 32 24 1 1 1 1 1 1 1 1 1 1 1 I/O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z I 32-bit data port of the external bus interface 24-bit address port of the external bus interface Read / write for external memory interface. R / W is high when a read is performed and low when a write is performed over the parallel interface. External peripheral I / O strobe for the external memory interface External memory-access strobe 0, byte enable 3 for 32-bit external memory interface and address pin for 8-bit and 16-bit external memory interface External memory-access strobe 0, byte enable 2 for 32-bit external memory interface and address pin for 8-bit external memory interface External memory-access strobe 0, byte enable 1 for the external memory interface External memory-access strobe 0, byte enable 0 for the external memory interface External memory-access strobe 1, byte enable 3 for 32-bit external memory interface and address pin for 8-bit and 16-bit external memory interface External memory-access strobe 1, byte enable 2 for 32-bit external memory interface and address pin for 8-bit external memory interface External memory-access strobe 1, byte enable 1 for the external memory interface External memory-access strobe 1, byte enable 0 for the external memory interface Ready. RDY indicates that the external device is prepared for an external memory interface transaction to complete. Hold signal for external memory interface. When HOLD is a logic low, any ongoing transaction is completed. A23 – A0, D31 – D0, IOSTRB, STRB0_Bx, STRB1_Bx, and R / W are placed in the high-impedance state, and all transactions over the external memory interface are held until HOLD becomes a logic high or the NOHOLD bit of the STRB0 bus-control register is set. Hold acknowledge for external memory interface. HOLDA is generated in response to a logic low on HOLD. HOLDA indicates that A23 – A0, D31 – D0, IOSTRB, STRB0_Bx, STRB1_Bx, and R / W are in the high-impedance state and that all transactions over the memory are held. HOLDA is high in response to a logic high of HOLD or when the NOHOLD bit of the external bus-control register is set. Program memory width select. When PRGW is a logic low, program is fetched as a single 32-bit word. When PRGW is a logic high, two 16-bit program fetches are performed to fetch a single 32-bit instruction word. The status of PRGW at device reset affects the reset value of the STRB0 and STRB1 bus-control register. S S S S S S S S S S S S H H H H H H H H H H H H R R R TYPE† DESCRIPTION CONDITIONS WHEN SIGNAL IS IN HIGH Z‡ HOLD 1 I HOLDA 1 O/Z S PRGW 1 I † I = input, O = output, Z = high-impedance state ‡ S = SHZ active, H = HOLD