SOT-23 Low Capacitance TVS

SL05T1 Series 300 Watt, SOT−23 Low Capacitance TVS for High Speed Line Protections This new family of TVS offers transient overvoltage protection with significantly reduced capacitance. The capacitance is lowered by integrating a compensating diode in series. This integrated solution offers ESD protection for high speed interfaces such as communication systems, computers, and computer peripherals. Features http://onsemi.com 2 1 • TVS Diode in Series with a Compensating Diode Offers <5 pF • • • • • Capacitance ESD Protection Meeting IEC 61000−4−2, 4−4, 4−5 Peak Power Rating of 300 W, 8 × 20 ms Bi−Direction Protection Can Be Achieved By Using Two Devices Flammability Rating UL 94 V−0 Pb−Free Packages are Available 3 (NC) MARKING DIAGRAM 3 1 2 SOT−23 (TO−236) CASE 318 STYLE 26 Lxx M G G Mechanical Characteristics: CASE: Void-free, transfer-molded, thermosetting plastic case FINISH: Corrosion resistant finish, easily solderable MAXIMUM CASE TEMPERATURE FOR SOLDERING PURPOSES: 260°C for 10 Seconds www.DataSheet4U.com Package designed for optimal automated board assembly Small package size for high density applications Available in 8 mm Tape and Reel Use the Device Number to order the 7 inch/3,000 unit reel. Replace the “T1” with “T3” in the Device Number to order the 13 inch/10,000 unit reel. Lxx = Device Code xx = 05, 15, or 24 M = Date Code* G = Pb−Free Package (Note: Microdot may be in either location) *Date Code orientation and/or overbar may vary depending upon manufacturing location. ORDERING INFORMATION Device SL05T1 SL05T1G SL15T1 SL15T1G SL24T1 SL24T1G Package SOT−23 SOT−23 (Pb−Free) SOT−23 SOT−23 (Pb−Free) SOT−23 SOT−23 (Pb−Free) SOT−23 SOT−23 SOT−23 Shipping † 3000/Tape & Reel 3000/Tape & Reel 3000/Tape & Reel 3000/Tape & Reel 3000/Tape & Reel 3000/Tape & Reel SL05T3 SL15T3 SL24T3 10,000/Tape & Reel 10,000/Tape & Reel 10,000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. DEVICE MARKING INFORMATION See specific marking information in the device marking column of the table on page 3 of this data sheet. © Semiconductor Components Industries, LLC, 2006 1 December, 2006 − Rev. 5 Publication Order Number: SL05T1/D SL05T1 Series MAXIMUM RATINGS Rating Peak Power Dissipation @ 8x20 usec (Note 1) @ TL ≤ 25°C IEC 61000−4−2 Level 4 Contact Discharge Air Discharge IEC 61000−4−4 EFT IEC 61000−4−5 Lightning Total Power Dissipation on FR−5 Board (Note 2) @ TA = 25°C Derate above 25°C Thermal Resistance Junction to Ambient Total Power Dissipation on Alumina Substrate (Note 3) @ TA = 25°C Derate above 25°C Thermal Resistance Junction−to−Ambient Junction and Storage Temperature Range Lead Solder Temperature − Maximum (10 Second Duration) Symbol Ppk Vpp Value 300 Unit W ±8 ±16 40 12 225 1.8 556 300 2.4 417 − 55 to +150 260 kV kV A A °mW° mW/°C °C/W °mW mW/°C °C/W °C °C °PD° RqJA °PD° RqJA TJ, Tstg TL Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Non−repetitive current pulse per Figure 2 2. FR−5 = 1.0 x 0.75 x 0.62 in. 3. Alumina = 0.4 x 0.3 x 0.024 in., 99.5% alumina ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) UNIDIRECTIONAL (Circuit tied to Pins 1 and 3 or 2 and 3) Symbol IPP VC VRWM IR VBR IT QVBR IF VF ZZT IZK ZZK Parameter Maximum Reverse Peak Pulse Current Clamping Voltage @ IPP Working Peak Reverse Voltage Maximum Reverse Leakage Current @ VRWM Breakdown Voltage @ IT Test Current Maximum Temperature Coefficient of VBR Forward Current Forward Voltage @ IF Maximum Zener Impedance @ IZT Reverse Current Maximum Zener Impedance @ IZK VC VBR VRWM IF I IR VF IT V IPP Uni−Directional TVS http://onsemi.com 2 SL05T1 Series ELECTRICAL CHARACTERISTICS Breakdown Voltage (Note 4) Device Marking L05 L15 L24 VRWM (V) 5.0 15 24 IR @ VRWM (mA) 20 1.0 1.0 VBR @ 1 mA (Volts) Min 6.0 16.7 26.7 Max 8.0 18.5 29 VC, Clamping Voltage (Note 5) @1A (V) 9.8 24 43 @5A (V) 11 30 55 Capacitance @ VR = 0 V, 1 MHz (pF) Typ 3.5 3.5 3.5 Max 5.0 5.0 5.0 Max IPP (A) 17 10 5.0 Device SL05 SL15 SL24 4. VBR measured at pulse test current of 1 mA at an ambient temperature of 25°C 5. Surge current waveform per Figure 2 TYPICAL CHARACTERISTICS 10 % OF PEAK PULSE CURRENT PPK, PEAK POWER (kW) 100 90 80 70 60 50 40 30 20 10 0 0 20 40 t, TIME (ms) 60 80 tP tr PEAK VALUE IRSM @ 8 ms PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms HALF VALUE IRSM/2 @ 20 ms 1 0.1 0.01 0.1 1 10 PULSE WIDTH (ms) 100 1000 Figure 1. Maximum Peak Power Rating Figure 2. 8 × 20 ms Pulse Waveform C, CAPACITANCE (pF), 1 MHz FREQ. 4 3.5 3 2.5 2 1.5 1 0.5 0 @ ZERO BIAS @ 50% VRWM @ VRWM SL05 SL15 SL24 LEAKAGE (mA) 10 1 SL05T1 0.1 0.01 −55 25 TEMPERATURE (°C) 150 Figure 3. Typical Junction Capacitance Figure 4. Typical Leakage Over Temperature http://onsemi.com 3 SL05T1 Series Applications Background This new family of TVS devices (SL05T1 series) are designed to protect sensitive electronics such as communications systems, computers, and computer peripherals against damage due to ESD conditions or transient voltage conditions. Because of their low capacitance value (less than 5 pF), they can be used in high speed I/O data lines. Low capacitance is achieved by integrating a compensating diode in series with the TVS which is basically based in the below theoretical principle: • Capacitance in parallel: CT = C1+C2+....+Cn • Capacitance in series: 1/CT = (1/C1)+(1/C2)+....+(1/Cn) The Figure 5 shows the integrated solution of the SL05T1 series device: 1 3 2 3 2 1 Figure 6. COMPENSATING DIODE TVS Figure 5. An alternative solution to protect unidirectional lines, is to connect a fast switching steering diode in parallel with the SL05T1 series device. When the steering diode is forward−biased, the TVS will avalanche and conduct in reverse direction. It is important to note that by adding a steering diode, the effective capacitance in the circuit will be increased, therefore the impact of adding a steering diode must be taken in consideration to establish whether the incremental capacitance will affect the circuit functionality or not. The Figure 7 shows the connection between the steering diode and the SL05T1 series device: SL05T1 DEVICE In the case that an over−voltage condition occurs in the I/O line protected by the SL05T1 series device, the TVS is reversed−biased while the compensation diode is forward−biased so the resulting current due to the transient voltage is drained to ground. If protection in both polarities is required, an additional device is connected in inverse−parallel with reference to the first one, the Figure 6 illustrates the inverse−parallel connection for bi−directional or unidirectional lines: STEERING DIODE Figure 7. Another typical application in which the SL05T1 series device can be utilized, is to protect multiple I/O lines. The protection in each of the I/O lines is achieved by connecting two devices in inverse−parallel. The Figure 8 illustrates how multiple I/O line protection is achieved: INPUT OUTPUT Figure 8. For optimizing the protection, it is recommended to use ground planes and short path lengths to minimize the PCB’s ground inductance. http://onsemi.com 4 SL05T1 Series PACKAGE DIMENSIONS SOT−23 (TO−236) CASE 318−08 ISSUE AN D 3 SEE VIEW C E 1 2 HE c b e q 0.25 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. 318−01 THRU −07 AND −09 OBSOLETE, NEW STANDARD 318−08. MILLIMETERS NOM MAX 1.00 1.11 0.06 0.10 0.44 0.50 0.13 0.18 2.90 3.04 1.30 1.40 1.90 2.04 0.20 0.30 0.54 0.69 2.40 2.64 INCHES NOM 0.040 0.002 0.018 0.005 0.114 0.051 0.075 0.008 0.021 0.094 A L A1 L1 VIEW C DIM A A1 b c D E e L L1 HE MIN 0.89 0.01 0.37 0.09 2.80 1.20 1.78 0.10 0.35 2.10 MIN 0.035 0.001 0.015 0.003 0.110 0.047 0.070 0.004 0.014 0.083 MAX 0.044 0.004 0.020 0.007 0.120 0.055 0.081 0.012 0.029 0.104 STYLE 26: PIN 1. CATHODE 2. ANODE 3. NO CONNECTION SOLDERING FOOTPRINT* 0.95 0.037 0.95 0.037 2.0 0.079 0.9 0.035 SCALE 10:1 0.8 0.031 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Thermal Clad is a registered trademark of the Bergquist Company. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intende