Wideband PLL FM Demodulator

SL1461SA Wideband PLL FM Demodulator Advance Information DS4049 - 1.2 December 1994 The SL1461SA is a wideband PLL FM demodulator, intended primarily for application in satellite tuners. The device contains all elements necessary, with the exception of external oscillator sustaining network and loop feedback components, to form a complete PLL system operating at frequencies up to 800MHz. An AFC with window adjust is provided, whose output signal can be used to correct for any frequency drift at the head end local oscillator. AFC PUMP AFC WINDOW ADJUST V EE OSCILLATOR + OSCILLATOR – AGC BIAS AGC OUTPUT RF INPUT 1 2 3 4 5 6 7 8 16 15 AFC OUTPUT V CC VIDEO FEEDBACK + VIDEO – VIDEO + VIDEO FEEDBACK – VIDEO OUTPUT RF INPUT SL1461SA 14 13 12 11 10 9 FEATURES s Single chip PLL system for wideband FM demodulation s Simple low component count application s Allows for application of threshold extension s Fully balanced low radiation design s High operating input sensivity s Improved VCO stability with variations in supply or temperature s AGC detect and bias adjust s 75Ω video output drive with low distortion levels s Dynamic self biasing analog AFC s Full ESD Protection* * Normal ESD handling procedures should be observed MP16 Fig.1 Pin connections - top view APPLICATIONS s Satellite receiver systems s Data communications Systems ORDERING INFORMATION SL1461SA/KG/MPAS AGC BIAS RF INPUTS AGC OUTPUT 6 8 9 7 14 12 13 11 VIDEO FEEDBACK + VIDEO + VIDEO – VIDEO FEEDBACK – VIDEO OUTPUT AFC PUMP AFC OUTPUT 10 1 LOCAL OSCILLATOR AFC WINDOW ADJUST 4 5 16 2 Fig.2 SL1461SA block diagram SL1461SA ELECTRICAL CHARACTERISTICS Tamb = -20°C to +80°C, VCC = +4.5V to +5.5V. The electrical characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. Characteristics Min. Supply current Operating frequency Input sensitivity Input overload VCO sensitivity (dF/dV) VCO linearity VCO supply stability VCO temperature stability Phase detector gain Loop amplifier input impedance Loop amplifier output impedance Loop amplifier open loop gain Loop amplifier gain bandwidth product Loop amplifier output swing Video drive output impedance Video drive: Luminance nonlinearity - differential gain - differential phase - intermodulation - signal/noise - Tilt - baseline distortion AGC output current AGC bias current AFC window current AFC charge pump current AFC leakage current AFC output saturation voltage 10 0 0 50 10 0.4 66 72 0.3 0.4 3 2 400 250 400 1.9 0.5 1.0 5 2.5 3 -40 % % Degree dB dB % % µA µA µA µA µA V With charge pump disabled AFC output enabled 400µA gives 1.5V deadband window 1KΩ load, See note 3 and 4 75KΩ load, See note 3 and 4 75KΩ load, See note 3 and 4 See notes 1, 3 and 4 1KΩ load, See note 2 and 4 1KΩ load, See note 3 and 4 1KΩ load, See note 3 and 4 Maximum load voltage drop 2V 55 75 450 0 25 32 25 2.0 20 0.5 0.25 570 25 38 240 1.2 95 700 39 300 -40 Value Typ. 36 Max. 40 800 mA MHz dBm dBm MHz/V % MHz/V KHz/°C V/rad V/rad Ω Ω dB MHz Vp-p Ω Refer to application in Fig. 3 Refer to application in Fig. 3; with 13.5MHz p-p deviation See note 5 See note 5 Differential loop filter Single ended loop filter Single ended Single ended Single ended Single ended Single ended Preamp limiting Units Conditions Note 1. Product of input modulation f 1 at 4.43MHz, 13.5MHz p–p deviation and f 2 at 6MHz p–p deviation, (PAL chroma and sound subcarriers). Note 2. Ratio of output video signal with input modulation at 1MHz, 13.5MHz p–p deviation, to output rms noise in 6MHz bandwidth with no input modulation. Note 3. Input test signal pre–emphasised video 13.5MHz p–p deviation. Output voltage 600mV pk–pk. Note 4. See page 3 Note 5. Assuming operating frequency of 479.5MHz set with VCC @ 5.0V and ambient temperature of +20°C. Only applies to Application shown in Fig. 3. also refer to Fig. 8. 2 SL1461SA TEST CONFIGURATION BASE BAND VIDEO 1V p–p TV SAT TEST TX ROHDE & SCHWARZ SFZ VIDEO GENERATOR ROHDE & SCHWARZ SGPF RF CARRIER FREQ 479.5MHz FM MODULATION 13.5MHz P–P PRE–EMPHASISED VIDEO MONTFORD TEST OVEN SL1461 TEST APPLICATION BOARD See Fig. 3 for details PRE EMPHASISED BASE BAND VIDEO VIDEO AMPLIFIER/ DE EMPHASISED NETWORK DE EMPHASISED BASE BAND VIDEO 1V p–p VIDEO ANALYSER ROHDE & SCHWARZ UAF The video drive characteristics measurements were made using the above test configuration. The maximum figures recorded in the Electrical Characteristics Table coincide with high temperatures and extremes of supply voltage. No adjustment to the recorded figures has been made to compensate for the effects of temperature on the external components of the application test board, in particular the varactor diodes. If operation of the device at high ambient temperatures is envisaged then attention to temperature compensation of the external circuitry will result in performance figures closer to the stated typical figures. Fig.2 SL1461SA block diagram ABSOLUTE MAXIMUM RATINGS All voltages are referred to VEE at 0V Characteristics Supply voltage RF input voltage RF input DC offset Oscillator ± DC offset Video ± DC offset Video feedback ± DC offset Video output DC offset AFC pump DC offset AFC disable DC offset AFC deadband DC offset AGC bias DC offset AGC output DC offset Storage temperature Junction temperature MP16 package thermal resistance, chip to ambient -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -55 Min. -0.3 Typ. 7 2.5 VCC+0.3 VCC+0.3 VCC+0.3 VCC+0.3 VCC+0.3 VCC+0.3 VCC+0.3 VCC+0.3 VCC+0.3 VCC+0.3 125 150 111 Max. V Vp-p V V V V V V V V V V °C °C °C/W Conditions 3 SL1461SA ABSOLUTE MAXIMUM RATINGS cont. All voltages are referred to VEE at 0V Characteristics MP16 package thermal resistance, chip to case Power consumption at 5.5V ESD protection - pins 1 to 15 ESD protection - Pin 16 2 1.7 Min. Typ. 41 250 Max. °C/W mW kV kV Mil-std-883 method 3015 class 1 Mil-std-883 method 3015 class 1 Conditions 2K AGC BIAS RV1 50K AFC WINDOW ADJUST RV2 C1 47nF C2 100nF R1 1 2 16 15 100nF 27K R6 C3 47 F C4 +5V 1nF C12 D1 BB515 C5 4K7 TP4 R5 1K2 R4 100pF C11 C10 TP2 VIDEO OUTPUT TP1 SL1461SA 3 4 14 13 12 11 10 9 BB515 470nF D2 TP3 4n7 C6 R2 5K1 4K7 R3 C7 1nF 5 6 7 8 100pF 1K2 C9 47 F C8 1nF RF INPUT Fig.3 Standard application circuit FUNCTIONAL DESCRIPTION The SL1461SA is a wideband PLL FM demodulator, optimised for application in satellite receiver systems and requiring a minimum external component count. It contains all the elements required for construction of a phase locked loop circuit, with the exception of tuning components for the local oscillator, and an AFC detector circuit for generation of error signal to correct for any frequency drift in the outdoor unit local oscillator. A block diagram is contained in Fig. 2 and the typical application in Fig. 3. The internal pin connections are contained in Fig.6/6a In normal applications the second satellite IF frequency of typically 402 or 479.5MHz is fed to the RF preamplifier, which has a working sensitivity of typically -40 dBm, depending on application and layout. The preamplifier contains an RF level detect circuit, which generates an AGC signal that can be used for controlling the gain of the IF amplifier stages, so maintaining a fixed level to the RF input of the SL1461SA, for optimum threshold performance. The bias point of the AGC circuit can be adjusted to cater for variation in AGC line voltage requirement and device input power. The typical AGC curves are shown in Fig. 9. It is recommended that the device is operated with an input signal between -30 and -35dBm. This ensures optimum linearity and threshold performance, and gives a good safety margin over the typical sensitivity of -40dBm. The output of the preamplifier is fed to the mixer section which is of balanced design for low radiation. In this stage the RF signal is mixed with the local oscillator frequency, which is generatedby an on–board oscillator. The oscillator block uses an external varactor tuned sustaining network and is optimised for high linearity over the normal deviation range. A typical frequency versus voltage characteristic for the oscillator is contained in Fig. 7. The loop output is designed to compensate for first order temperature variation effects; the typical stability is shown in Fig. 8 The output of the mixer is then fed to the loop amplifier around which feedback is applied to determine loop transfer characteristic . Feedback can be applied either in differential or single ended mode; if the appropriate phase detector gains are assumed in calculating loop filters, both modes should give the same loop response. The loop amplifier drives a 75Ω output impedance buffer amplifier, which can either be connected to a 75Ω load or used to drive a high input impedance stage giving greater linearity and approximately 6dB higher demodulated signal output level. 4 SL1461SA DESIGN OF PLL LOOP PARAMETERS R2 C1 BASEBAND OUTPUT GAIN = KD VOLT/RAD RF INPUT R1 GAIN = K0 RAD SEC/VOLT VCO Fig.4 The SL1461SA is normally used as a type 1 second order loop and can be represented by the above diagram. For such a system the following parameters apply; where: K0 is the VCO gain in radian seconds per volt KD is the phase detector gain in volts per radian n is the natural loop bandwidth is the loop damping factor R1 is loop amplifier input impedance Note: K0 is dependant on sensitivity of VCO used. KD = 0.25V/rad single ended, 0.5V/rad differential 1 2 and K 0K D 1 2 n From these factors the loop 3dB bandwidth can be determined from the following expression; 2 2 n AFC FACILITY The SL1461SA contains an analog frequency error detect circuit, which generates DC voltage proportional to the integral of frequency error. If the incident RF is high then the AFC voltage increases, if low then the voltage decreases. The AFC voltage can