Demonstration Board

www.DataSheet4U.com SiP11203DB Vishay Siliconix SiP11203 Demonstration Board DEMONSTRATION BOARD TEST SETUP This demonstration board test setup information details the test procedure for using the SiP11203 demonstration board and its associated host board. The demonstration board is plugged vertically into the host board. Only one orientation is possible for correct plugin. The input and output power leads and an optional enable lead are wired into the host board connectors as shown in Figure 1. A mechanical toggle switch is also available on the host board for manual enabling and disabling of the demonstration board. The host board is configured by default for manual switch toggling of enable/disable. If an electrical control signal is preferred, this can be wired into the enable connector J2. However, in this case the zero ohm link connected in the R4 position must be removed and reconnected in the R1 position, which is vacant by default. A 5 V input to the enable pin disables the demonstration board and a 0 V or open circuit input signal causes the demonstration board to be enabled. Test pins are available on the host board, at the input, output, and enable pins, for the easy connection of scope probes. These wiring connections are depicted in Figure 1. The input connections should be wired as closely as possible to the power supply, using cable rated at 2 A or more. However, lead lengths of up to a meter or two are probably acceptable. If the leads are significantly longer, a second input decoupling capacitor should be connected in position C1, which is left blank by default. At the load side, four 8 A rated wires should be connected from both +Vout and -Vout terminals to the load. The Vsense terminals can be connected remotely to the load terminals for good regulation at the load, but this is not essential, as the Vsense terminals are connected to the output terminals through 4.7 Ω resistors on the demonstration board. A small fan should be placed adjacent to the host board, blowing cooling air over both vertical faces of the demonstration board. There is over temperature protection within the demonstration board, so the system will function without fan cooling, but the demonstration board will disable operation if the PCB temperature exceeds 85 ºC, and will re-enable once the temperature drops to 75 ºC. The rated input voltage range is 36 V - 75 V, and the converter can operate at input voltage levels up to 100 V for 100 ms. The maximum rated load is 50 W. The output voltage is regulated to 3.3 V with an output load current range of 0 A - 15 A. FEATURES • High efficiency, > 87 % at full rated load current • Delivers up to 15 amps of output current with minimal de-rating - no heat sink required • Wide input voltage range: 35 V - 75 V, with 100 V 100 ms input voltage transient capability • No minimum load requirement means no preload resistors required • Remote sense for the output voltage compensates for output distribution drops • On/Off control referenced to input side • Input under-voltage lockout disables converter at low input voltage conditions • Output short circuit protection protects converter and load from permanent damage and consequent hazardous conditions • Output over-voltage protection protects load from damaging voltages • Thermal shutdown protects converter from abnormal environmental conditions To load Airflow Direction Enable (optional) VinVin+ Figure 1. SiP11203 Test Board Layout The information shown here is a preliminary product proposal, not a commercial product data sheet. Vishay Siliconix is not committed to produce this or any similar product. This information should not be used for design purposes, nor construed as an offer to furnish or sell such products Document Number: 74254 S-60997–Rev. A, 12-Jun-06 www.vishay.com 1 SiP11203DB Vishay Siliconix DEMONSTRATION BOARD INFORMATION The demonstration board is an 8-layer board in the eighth-brick form factor, manufactured in 2 oz copper. The circuit schematics for the SiP11203 demonstration board are illustrated in Figure 2 and Figure 3. Power Conversion Circuit The primary power circuit is a half-bridge configuration with a 4:1 turns ratio transformer, T2, connected between the switching pole of the half-bridge and the center tap of the capacitive input filter. The half-bridge capacitors C10 to C17 are configured as two series-connected banks of four parallel-connected 1 µF ceramic capacitors. Resistors R20 and R21 provide voltage balancing and discharge paths for the capacitor banks. The primary side half-bridge circuit is driven using the Si9122 controller IC. This generates both the primary MOSFET drive signals as well as the timing signals for the secondary side synchronous MOSFETs. These timing signals, SRL and SRH, are coupled to the secondary through the pulse transformer T1. The SiP11203 uses the timing information to drive the secondary synchronous MOSFETs Q3 to Q6. The secondary side synchronous MOSFETs rectify the center-tapped transformer secondary voltage, the output of which is filtered by the LC-filter L1C28-C31. L1 is a 900 nH inductor, C28 is a 22 µF tantalum capacitor and C31 is a 100 µF ceramic capacitor. RCD snubbers are placed across the synchronous rectifier MOSFETs in order to clamp the secondary leakage inductance voltage spike and reduce switching losses. Some of the main switching circuit waveforms are plotted in Figure 4. The converter efficiency over the line and load range is depicted in Figure 5. Note that these efficiency readings do not take account of the voltage drops across the plug-in pins of the demonstration board. Bias Supply The primary bias supply, VCC, is a 10.4 V supply that is generated from an auxiliary winding, L1-B of the output filter inductor. The auxiliary winding turns ratio is 3.333:1, resulting in an auxiliary winding voltage of approximately 11 V during the inductor current rampdown period. This voltage is rectified and filtered by diode D4 and capacitors C23 and C26. During startup and other conditions such as short-circuited output, the primary bias voltage is supplied by means of a 9.1 V linear pre-regulator on the Si9122 controller. An external PNP pre-regulator transistor Q8 is provided to divert the main power dissipation away from the Si9122 during the period when the 9.1 V bias is being utilised. The rise of VCC and VO during startup is depicted in Figure 6 (a). It is clear that converter operation commences when VCC reaches 9.1 V and, the change to the auxiliary bias level can also be seen. Figure 2. SiP11203 Demonstration Board Primary Side Schematic www.vishay.com 2 Document Number: 74254 S-60997–Rev. A, 12-Jun-06 SiP11203DB Vishay Siliconix Figure 3. SiP11203 Demonstration Board Secondary Side Schematic Primary Gate drive Waveform (10 V/DIV) Input of Pulse Transformer (10 V/DIV) Primary Switching Waveform (20 V/DIV) Output of Pulse Transformer (5 V/DIV) Output of SiP11203 Driver (5 V/DIV) Output of SiP11203 Driver (5 V/DIV) Drain of Secondary MOSFET (10 V/DIV) 1.00 µS/DIV (a) Drain of Secondary MOSFET (10 V/DIV) 1.00 µS/DIV (b) Figure 4. (a) Primary switching waveforms and the secondary switching waveforms. (b) The gate driving waveform and the secondary switching waveform. Document Number: 74254 S-60997–Rev. A, 12-Jun-06 www.vishay.com 3 SiP11203DB Vishay Siliconix 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 2A 4A 35 Vin 48 Vin Eff (%) 75 Vin 6A 8 A 10 A Io (A) 12 A 14 A 15 A Figure 5. Converter efficiency over line voltage and load range The secondary bias supply (VIN on the SiP11203) is provided from VCC via the timing signals SRH and SRL generated by the Si9122. These timing signals drive the positive and negative terminals of the primary winding of pulse transformer T1. This transformer has a step-down ratio of 4:3 for each secondary winding. The secondary windings are center tapped, with a capacitive filter placed at the center tap point, and rectifier diodes anode-connected to ground, connected to each end of the secondary windings. This arrangement means that the timing information is coupled to the SiP11203, while a bias voltage is also available at the center-tap to power the SiP11203. This bias voltage VIN is used to power the output drivers OUTA and OUTB. It is also internally regulated to a 5 V bias, VL, which powers the other internal circuitry on the SiP11203. The voltage on one of the pulse transformer secondary windings wrt ground is shown in Figure 6 (b). It can be seen from this that the center-tap voltage, which provides the VIN supply to the SiP11203, is equal to the average value of the secondary voltage. Output of pulse tansformer (2 V/DIV) Primary VCC Start Up Waveform (2 V/DIV) VIN for SiP11203 (2 V/DIV) Output Voltage Start Up Waveform (1 V/DIV) 1.00 mS/DIV (a) 1.00 µS/DIV (b) Figure 6. (a)VCC, VO, during startup (b)Pulse Transformer Secondary Voltage, Pulse Transformer Center-Tap Voltage, VIN. Magnetic Component The main power transformer structure is illustrated in Figure 7. The multilayer PCB layout is described in Table 1. The primary magnetizing inductance is between 11 µH and 15 µH, and the turns ratio is 4:1:1. The core is a combination of an E14/3.5/5 core and its associated I-plate in 3F3 material. The output filter inductor structure is illustrated in Figure 8 and the multilayer PCB layout is described in Table 2. The inductor has 2 sections of 3 turns connected in parallel, with a custom ground center gap to yield an inductance value between 850 nH and 900 nH. The auxiliary winding is constructed of 10 turns, divided between 2 layers, resulting in a 10:3 turns ratio between the auxiliary and main windings. The core is a combination of an E14/ 3.5/5 core and its associated I-plate in 3F3 material. www.vishay.com 4 P1 P2 Primary P3 S1 S2 Secondary S3 S4 Secondary P4 Figure 7. Power Transformer Structure Document Number: 74254 S-