Bi-Directional P-Channel 20-V (D-S) MOSFET

www.DataSheet4U.com SPICE Device Model Si8901EDB Vishay Siliconix Bi-Directional P-Channel 20-V (D-S) MOSFET CHARACTERISTICS • P-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit mode is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-to-5V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 72950 19-Apr-04 www.vishay.com 1 www.DataSheet4U.com SPICE Device Model Si8901EDB Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current b Symbol Test Conditions Simulated Data 0.49 42 0.046 0.060 0.075 6.2 Measured Data Unit VGS(th) ID(on) VSS = VGS, ID = − 250µA VSS = − 5V, VGS = − 4.5V VGS = − 4.5V, ISS = − 1A V A 0.048 0.062 0.081 7 S Ω Drain-Source On-State Resistanceb rDS(on) VGS = − 2.5V, ISS = − 1A VGS = − 1.8V, ISS = − 1A Forward Transconductanceb gfs VSS = −10V, ISS = − 1A Dynamic Rise Time a Turn-On Delay Time td(on) tr td(off) tf VSS = − 10V, RL = 10Ω ISS ≅ − 1A, VGEN = − 4.5V, RG = 6Ω 2 2 2.1 7 2.3 2.2 1.3 9 µs Turn-Off Delay Time Fall Time Notes a. Guaranteed by design, not subject to production testing. b. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. www.vishay.com 2 Document Number: 72950 19-Apr-04 www.DataSheet4U.com SPICE Device Model Si8901EDB Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 72950 19-Apr-04 www.vishay.com 3