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SPICE Device Model Si5943DU Vishay Siliconix Dual P-Channel 12-V (D-S) MOSFET
CHARACTERISTICS
• P-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics
DESCRIPTION
The attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-V to 5-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 74177 S-61262Rev. A, 24-Jul-06 www.vishay.com 1
SPICE Device Model Si5943DU Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static
Gate Threshold Voltage On-State Drain Current
a
Symbol
Test Condition
Simulated Data
0.75 73 0.052 0.075 0.106 18 −0.85
Measured Data
Unit
VGS(th) ID(on)
VDS = VGS, ID = −250 µA VDS ≤ −5 V, VGS = −4.5 V VGS = −4.5 V, ID = −3.6 A
V A 0.053 0.073 0.098 11 −0.80 S V Ω
Drain-Source On-State Resistancea
rDS(on)
VGS = −2.5 V, ID = −3.1 A VGS = −1.8 V, ID = −0.83 A
Forward Transconductancea Diode Forward Voltage
a
gfs VSD
VDS = −6 V, ID = −3.6 A IS = −4 A
Dynamic
b
Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge
Ciss Coss Crss Qg Qgs Qgd VDS = −6 V, VGS = −8 V, ID = −5A VDS = −6 V, VGS = −4.5 V, ID = −5 A VDS = −6 V, VGS = 0 V, f = 1 MHz
624 169 118 8 5 0.90 1.65
460 170 115 10 6 0.90 1.65 nC pF
Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production testing.
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Document Number: 74177 S-61262Rev. A, 24-Jul-06
SPICE Device Model Si5943DU Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
Document Number: 74177 S-61262Rev. A, 24-Jul-06
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