OTP 4K x 4-Bit Micro-Controller

www.DataSheet4U.com SH69P25 PRELIMINARY Features SH6610C-based single-chip 4-bit micro-controller OTPROM: 4096 X 16 bits RAM: 160 X 4 bits (data memory) Operation voltage: 2.4V - 6.0V (typical 3.0V or 5.0V) 22 CMOS bi-directional I/O pins Built in pull-up and pull-low resistor for PortA ~ PortF 4-level subroutine nesting (including interrupts) One 8-bit auto re-load timer/counter Warm-up timer for power on reset Powerful interrupt sources: - Internal interrupt (Timer0) - External interrupts: PortB & PortC (rising/falling edge) Oscillator (OTP option) - X`tal oscillator: 32.768kHz - 4MHz - Ceramic resonator: 400k - 4MHz - RC oscillator:400k - 4MHz - External clock: 30k - 4MHz Instruction cycle time: - 4/32.768kHz(122us) for 32.768kHz OSC clock - 4/4MHz (1us) for 4MHz OSC clock Two low power operation modes: HALT and STOP Built-in watch dog timer (OTP option) Built-in power on reset Two LPD level(OTP option) - High level: 4.0V - Low level: 2.5V OTP type &Code protection OTP 4-bit Microcontroller General Description SH69P25 is a 4-bit micro controller. This chip integrates the SH6610C 4-bit CPU core with SRAM, 4K OTPROM, Timer and I/O Ports. Pin Configuration PE2 PE3 PF1 PA2 PA3 T0 RESET GND PB0 PB1 PB2 PB3 PD0 PD1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PE1 PE0 PF0 PA1 PA0 OSCI OSCO VDD PC3 PC2 PC1 PC0 PD3 PD2 SH69P25 1 V1.01 www.DataSheet4U.com SH69P25 Block Diagram RESET OSCO OSCI OSC WDTEN RC RESET WATCHDOG TIMER PRESCLALER CPU PORTA ( 4-BITS ) PORTA [0:3] PORTB ( 4-BITS ) Power on PORTB [0:3] LPD CTL REG. LPDON T0 8-BITS TIMER ( Up counter ) OTPROM 4096*16 BITS PORTE ( 4-BITS ) TIMER INTERRUPT DATA RAM 160*4 BITS PORTF ( 2-BITS ) PORTF [0:1] PORTE [0:3] PORTD (4-BITS ) PORTD [0:3] PORTC [0:3] PORTC ( 4-BITS ) 2 www.DataSheet4U.com SH69P25 Pin Description(Normal mode) Pin No. 27, 28, 1, 2 26, 3 24, 25, 4, 5 6 7 8 9 - 12 13- 16 17 - 20 21 22 23 Designation PE[0:3] PF[0:1] PA[0:3] T0 RESET GND PB[0:3] PD[0:3] PC[0:3] VDD OSCO OSCI I/O I/O I/O I/O I I P I/O I/O I/O P O I Bit programmable I/O Bit programmable I/O Bit programmable I/O. Timer Clock/Counter input pin. (Schmitt trigger input) Reset input (active low, Schmitt trigger input). Ground pin Bit programmable I/O. Vector Interrupt (Active rising or falling edge by system register setup) Bit programmable I/O Bit programmable I/O. Vector Interrupt (Active rising or falling edge by system register setup) Power supply pin OSC output pin. No output in RC mode OSC input pin, connected to a crystal, ceramic or external resistor. Descriptions OTP Programming Pin Description (OTP program mode) Pin No. 21 7 8 23 24 Symbol VDD VPP GND SCK SDA I/O P P P I I/O Shared by VDD RESET GND OSCI PA[0] Description Programming Power supply (+5.5V) Programming high voltage Power supply (+10.5V) Ground Programming Clock input pin Programming Data pin 3 www.DataSheet4U.com SH69P25 Function Description 1. CPU The CPU contains the following function blocks: Program Counter, Arithmetic Logic Unit (ALU), Carry Flag, Accumulator, Table Branch Register, Data Pointer (INX, DPH, DPM, and DPL), and the Stack. 1.1. PC (Program Counter) The Program Counter is used to address the 4K program ROM. It consists of 12-bits: the Page Register (PC11), and the Ripple Carry Counter (PC10, PC9, PC8, PC7, PC6, PC5, PC4, PC3, PC2, PC1, PC0). The program counter normally increases by one (+1) with every execution of an instruction except in the following cases: (1) When executing a jump instruction (such as JMP, BA0, BAC), (2) When executing a subroutine call instruction (CALL), (3) When an interrupt occurs, (4) When the chip is in the INITIAL RESET mode. The program counter is loaded with data corresponding to each instruction. The unconditional jump instruction (JMP) can be set at 1-bit page register for higher than 2K. 1.2. ALU and CY ALU performs arithmetic and logic operations. The ALU provides the following functions: Binary addition/subtraction (ADC, SBC, ADD, SUB, ADI, SBI) Decimal adjustment for addition/subtraction (DAA, DAS) Logic operations (AND, EOR, OR, ANDIM, EORIM, ORIM) Decision (BA0, BA1, BA2, BA3, BAZ, BAC) Logic Shift (SHR) The Carry Flag (CY) holds the ALU overflow which the arithmetic operation generates. During an interrupt servicing or call instruction, the carry flag is pushed into the stack and retrieved back from the stack by the RTNI instruction. It is unaffected by the RTNW instruction. 1.3. Accumulator The Accumulator is a 4-bit register holding the results of the arithmetic logic unit. In conjunction with the ALU, data transfer between the accumulator and system register or data memory can be performed. 1.4. Stack A group of registers are used to save the contents of CY & PC (10-0) sequentially with each subroutine call or interrupt. It is organized into 13 bits X 4 levels. The MSB is saved for CY. 4 levels are the maximum allowed for subroutine calls and interrupts. The contents of the Stack are returned sequentially to the PC with the return instructions (RTNI/RTNW). The stack is operated on a first-in, last-out basis. This 4-level nesting includes both subroutine calls and interrupts requests. Note that program execution may enter an abnormal state if the number of calls and interrupt requests exceed 4, and the bottom of the stack will be shifted out. 2. OTPROM The SH69P25 can address up to 4096 X 16 bit words of program area from $000 to $FFF. Service routine as starting vector address. Address $000H $001H $002H $003H $004H Instruction JMP Instruction NOP JMP Instruction NOP JMP Instruction Remarks Jump to RESET service routine Reserved Jump to TIMER0 service routine Reserved Jump to PBC service routine 4 www.DataSheet4U.com SH69P25 3. RAM The built-in RAM consists of general-purpose data memory and the system register. Direct addressing in one instruction can access both data memory and the system register. The following is the memory allocation map: $000 - $01F: System register and I/O. $020 - $0BF: Data memory (160 X 4 bits, divided into 2 banks. $020 - $07F: bank0, $080 - $0BF: bank1). (a) The Configuration of the System Register Address $00 $01 $02 $03 $04 $05 $06-$07 $08 $09 $0A $0B $0C $0D $0E $0F $10 $11 $12 $13 - $14 $15 $16 $17 $18 $19 $1A $1B $1C $1D $1E $1F PULLEN Bit3 TL0.3 TH0.3 PA.3 PB.3 PC.3 PD.3 PE.3 TBR.3 INX.3 DPL.3 Bit2 IET0 IRQT0 TM0.2 TL0.2 TH0.2 PA.2 PB.2 PC.2 PD.2 PE.2 TBR.2 INX.2 DPL.2 DPM.2 DPH.2 Bit1 TM0.1 TL0.1 TH0.1 PA.1 PB.1 PC.1 PD.1 PE.1 PF.1 TBR.1 INX.1 DPL.1 DPM.1 DPH.1 Bit0 IEP IRQP TM0.0 TL0.0 TH0.0 PA.0 PB.0 PC.0 PD.0 PE.0 PF.0 TBR.0 INX.0 DPL.0 DPM.0 DPH.0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Interrupt enable flags Interrupt request flags Timer0 Mode register (Prescaler) Reserved Timer0 load/counter register low digit Timer0 load/counter register high digit Reserved PORTA PORTB PORTC PORTD PORTE PORTF Table Branch Register Pseudo index register Data pointer for INX low nibble Data pointer for INX middle nibble Data pointer for INX high nibble Reserved Bit1:PBC interrupt rising / failing edge set Bit2:Port pull-hi/low set Bit3: Port pull-up/low enable control PA3OUT PA2OUT PA1OUT PA0OUT PB3OUT PB2OUT PB1OUT PB0OUT PC3OUT PC2OUT PC1OUT PC0OUT PD3OUT PD2OUT PD1OUT PD0OUT PE3OUT PE2OUT PE1OUT PE0OUT WDT PF1OUT T0S PF0OUT T0E R/W R/W R/W R/W R/W R/W R/W W Set PORTA as an output port Set PORTB as an output port Set PORTC as an output port Set PORTD as an output port Set PORTE as an output port Set PORTF as an output port Bit0: T0 signal edge; Bit1: T0 signal source Reserved Bit3: WDT timer reset (write 1 to reset WDT) Reserved Remarks PH/PL PBCFR - R/W * System Register $00 - $12 (except $07H) refer to "SH6610C User manual". 5 www.DataSheet4U.com SH69P25 (b) System Register state: Bit 3 $00 $01 $02 $03 $04 $05 $06-$07 $08 $09 $0A $0B $0C $0D $0E $0F $10 $11 $12 $13 - $14 $15 $16 $17 $18 $19 $1A $1B $1C $1D $1E $1F PULLEN PA3OUT PB3OUT PC3OUT PD3OUT PE3OUT WDT PH/PL PA2OUT PB2OUT PC2OUT PD2OUT PE2OUT PBCFR PA1OUT PB1OUT PC1OUT PD1OUT PE1OUT PF1OUT T0S PA0OUT PB0OUT PC0OUT PD0OUT PE0OUT PF0OUT T0E TL0.3 TH0.3 PA.3 PB.3 PC.3 PD.3 PE.3 TBR.3 INX.3 DPL.3 Bit 2 IET0 IRQT0 TM0.2 TL0.2 TH0.2 PA.2 PB.2 PC.2 PD.2 PE.2 TBR.2 INX.2 DPL.2 DPM.2 DPH.2 Bit 1 TM0.1 TL0.1 TH0.1 PA.1 PB.1 PC.1 PD.1 PE.1 PF.1 TBR.1 INX.1 DPL.1 DPM.1 DPH.1 Bit 0 IEP IRQP TM0.0 TL0.0 TH0.0 PA.0 PB.0 PC.0 PD.0 PE.0 PF.0 TBR.0 INX.0 DPL.0 DPM.0 DPH.0 Power On Reset /Pin Reset / Low Voltage Reset -0-0 -0-0 - 000 0000 0000 1111 1111 1111 1111 1111 - -11 xxxx xxxx xxxx -xxx -xxx 010 0000 0000 0000 0000 0000 - - 00 - - 00 WDT Reset -0-0 -0-0 - 000 0000 0000 1111 1111 1111 1111 1111 - -11 uuuu uuuu uuuu -uuu -uuu 010 0000 0000 0000 0000 0000 - - 00 - - 00 - Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. 6 www.DataSheet4U.com SH69P25 (c) Others initial state: Others Program Counter (PC) CY Accumulator (AC) Data Memory After any Reset $000 Undefined Undefined Undefined 4. Low Power Detection (LPD) The LPD function is used to monitor the supply voltage and applies an internal reset in the micro-controller at the time of battery replacement. If the applied circuit satisfies the following conditions, the LPD can be incorporated using software control. - Power supply voltage VDD = 2.4 to 6.0 V 4.1 Functions of the LPD Circuit The LPD function is selected by OTP option. The LPD circuit has the following functions: - It generates an internal reset signal when VDD ≤ VLPD and t ≥ tLPD - It cancels the internal reset signal when VDD > VLPD or VDD ≤ VLPD and t < tLPD Here, VDD: power supply voltage, VLPD: LPD detect voltage, There are two level selected by OTP option: Low level: 2.3~2.7V, typical 2.5V High level: 3.8~4.2V, typical 4.0V tLPD: 100£g s~500£g s, typical 300£g s LPD can be enabled or disabled permanently by OTP option. 7 www.DataSheet4U.com SH69P25 5. I/O Ports The SH69P25 provides 22 I/O pins. When every I/O is used as an input port, the port control