PULSE WIDTH MODULATION CONTROL CIRCUIT

SG3526 Pulse Width Modulation Control Circuit The SG3526 is a high performance pulse width modulator integrated circuit intended for fixed frequency switching regulators and other power control applications. Functions included in this IC are a temperature compensated voltage reference, sawtooth oscillator, error amplifier, pulse width modulator, pulse metering and steering logic, and two high current totem pole outputs ideally suited for driving the capacitance of power FETs at high speeds. Additional protective features include soft start and undervoltage lockout, digital current limiting, double pulse inhibit, adjustable dead time and a data latch for single pulse metering. All digital control ports are TTL and B−series CMOS compatible. Active low logic design allows easy wired−OR connections for maximum flexibility. The versatility of this device enables implementation in single−ended or push−pull switching regulators that are transformerless or transformer coupled. The SG3526 is specified over a junction temperature range of 0° to +125°C. • 8.0 V to 35 V Operation • 5.0 V ±1% Trimmed Reference • 1.0 Hz to 400 kHz Oscillator Range • Dual Source/Sink Current Outputs: ±100 mA www.DataSheet4U.com • Digital Current Limiting • Programmable Dead Time • Undervoltage Lockout • Single Pulse Metering • Programmable Soft−Start • Wide Current Limit Common Mode Range • Guaranteed 6 Unit Synchronization Vref VCC Ground Sync RDeadtime RT CT Reset CSoft−Start 18 17 Reference Regulator 15 12 11 9 Oscillator 10 5 4 3 VCC + − − + SQ R Q Under− Voltage Lockout To Internal Circuitry 14 VC 13 Output A Soft Start Memory F/F S RQ Toggle F/F Q T Q 16 Output B http://onsemi.com MARKING DIAGRAM 18 PDIP−18 N SUFFIX CASE 707 1 A WL YY WW 1 = Assembly Location = Wafer Lot = Year = Work Week SG3526N AWLYYWW 18 PIN CONNECTIONS +Error −Error Compensation CSoft−Start Reset −CS +CS Shutdown RT 1 2 3 4 5 6 7 8 9 (Top View) 18 Vref 17 VCC 16 Output B 15 Ground 14 VC 13 Output A 12 Sync 11 RDeadtime 10 CT ORDERING INFORMATION Device SG3526N Package PDIP−18 Shipping 20 Units/Rail Compensation +Error −Error +C.S. −C.S. Shutdown 1 2 Amp 100 mV 7 + 6 − 8 Metering F/F Figure 1. Representative Block Diagram © Semiconductor Components Industries, LLC, 2006 July, 2006 − Rev. 4 1 Publication Order Number: SG3526/D SG3526 MAXIMUM RATINGS (Note 1) Rating Supply Voltage Collector Supply Voltage Logic Inputs Analog Inputs Output Current, Source or Sink Reference Load Current (VCC = 40 V, Note 2) Logic Sink Current Power Dissipation TA = +25°C (Note 3) TC = +25°C (Note 4) Thermal Resistance Junction−to−Air Thermal Resistance Junction−to−Case Operating Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10 Seconds) PD IO Iref Symbol VCC VC Value +40 +40 −0.3 to +5.5 −0.3 to VCC ±200 50 15 1000 3000 100 42 +150 −65 to +150 ±300 °C/W °C/W °C °C °C Unit Vdc Vdc V V mA mA mA mW RθJA RθJC TJ Tstg TSolder RECOMMENDED OPERATING CONDITIONS Characteristics Supply Voltage Collector Supply Voltage Output Sink/Source Current (Each Output) Reference Load Current Oscillator Frequency Range Oscillator Timing Resistor Oscillator Timing Capacitor Available Deadtime Range (40 kHz) Operating Junction Temperature Range 1. 2. 3. 4. Values beyond which damage may occur. Maximum junction temperature must be observed. Derate at 10 mW/°C for ambient temperatures above +50°C. Derate at 24 mW/°C for case temperatures above +25°C. Symbol VCC VC IO Iref fosc RT CT − TJ Min 8.0 4.5 0 0 0.001 2.0 0.001 3.0 0 Max 35 35 ±100 20 400 150 20 50 +125 Unit Vdc Vdc mA mA kHz kΩ μF % °C http://onsemi.com 2 SG3526 ELECTRICAL CHARACTERISTICS (VCC = +15 Vdc, TJ = Tlow to Thigh [Note 6], unless otherwise noted.) Characteristics REFERENCE SECTION (Note 7) Reference Output Voltage (TJ = +25°C) Line Regulation (+8.0 V ≤ VCC ≤ +35 V) Load Regulation (0 mA ≤ IL ≤ 20 mA) Temperature Stability Total Reference Output Voltage Variation (+8.0 V ≤ VCC ≤ +35 V, 0 mA ≤ IL ≤ 20 mA) Short Circuit Current (Vref = 0 V) (Note 5) UNDERVOLTAGE LOCKOUT Reset Output Voltage (Vref = +3.8 V) Reset Output Voltage (Vref = +4.8 V) OSCILLATOR SECTION (Note 8) Initial Accuracy (TJ = +25°C) Frequency Stability over Power Supply Range (+8.0 V ≤ VCC ≤ +35 V) Frequency Stability over Temperature (ΔTJ = Tlow to Thigh) Minimum Frequency (RT = 150 kΩ, CT = 20 μF) Maximum Frequency (RT = 2.0 kΩ, CT = 0.001 μF) Sawtooth Peak Voltage (VCC = +35 V) Sawtooth Valley Voltage (VCC = +8.0 V) ERROR AMPLIFIER SECTION (Note 9) Input Offset Voltage (RS ≤ 2.0 kΩ) Input Bias Current Input Offset Current DC Open Loop Gain (RL ≥ 10 MΩ) High Output Voltage (VPin 1−VPin 2 ≥ +150 mV, Isource = 100 μA) Low Output Voltage (VPin 2−VPin 1 ≥ +150 mV, Isink = 100 μA) Common Mode Rejection Ratio (RS ≤ 2.0 kΩ) Power Supply Rejection Ratio (+12 V ≤ VCC ≤ +18 V) 5. 6. 7. 8. 9. Maximum junction temperature must be observed. Thigh = +125°C Tlow = 0°C IL = 0 mA unless otherwise noted. fosc = 40 kHz (RT = 4.12 kΩ ± 1%, CT = 0.01 μF ± 1%, RD = 0 Ω) 0 V ≤ VCM ≤ +5.2 V. VIO IIB IIO AVOL VOH VOL CMRR PSRR − − − 60 3.6 − 70 66 2.0 −350 35 72 4.2 0.2 94 80 10 −2000 200 − − 0.4 − − mV nA nA dB V V dB dB Δfosc Δ V Δfosc Δ TJ fmin fmax Vosc(P) Vosc(V) − 400 − 0.45 0.5 − 3.0 0.8 − − 3.5 − Hz kHz V V − − − ±3.0 0.5 2.0 ±8.0 1.0 − % % % − 2.4 0.2 4.8 0.4 − V V Vref Regline Regload ΔVref/ΔT ΔVref ISC 4.90 − − − 4.85 25 5.00 10 10 10 5.00 80 5.10 30 50 − 5.15 125 V mV mV mV V mA Symbol Min Typ Max Unit CC http://onsemi.com 3 SG3526 ELECTRICAL CHARACTERISTICS (continued) Characteristics PWM COMPARATOR SECTION (Note 10) Minimum Duty Cycle (VCompensation = +0.4 V) Maximum Duty Cycle (VCompensation = +3.6 V) DIGITAL PORTS (SYNC, SHUTDOWN, RESET) Output Voltage (High Logic Level) (Isource = 40 μA) (Low Logic Level) (Isink = 3.6 mA) Input Current ⎯ High Logic Level (High Logic Level) (VIH = +2.4 V) (Low Logic Level) (VIL = +0.4 V) CURRENT LIMIT COMPARATOR SECTION (Note 12) Sense Voltage (RS ≤ 50 Ω) Input Bias Current SOFT−START SECTION Error Clamp Voltage (Reset = +0.4 V) CSoft−Start Charging Current (Reset = +2.4 V) OUTPUT DRIVERS (Each Output, VC = +15 Vdc, unless otherwise noted.) Output High Level Isource = 20 mA Isource = 100 mA Output Low Level Isink = 20 mA Isink = 100 mA Collector Leakage, VC = +40 V Rise Time (CL = 1000 pF) Fall Time (CL = 1000 pF) Supply Current (Shutdown = +0.4 V, VCC = +35 V, RT = 4.12 kΩ) 10. fosc = 40 kHz (RT = 4.12 kΩ ± 1%, CT = 0.01 μF ± 1%, RD = 0 Ω) 11. 0 V ≤ VCM ≤ +5.2 V 12. 0 V ≤ VCM ≤ +12 V VOH V 12.5 12 − − − − − − 13.5 13 0.2 1.2 50 0.3 0.1 18 − − V 0.3 2.0 150 0.6 0.2 30 μA μs μs mA ICS − 50 0.1 100 0.4 150 V μA Vsense IIB 80 − 100 −3.0 120 −10 mV μA V VOH VOL IIH IIL 2.4 − − − 4.0 0.2 −125 −225 − 0.4 −200 −360 μA DCmin DCmax − 45 − 49 0 − % % Symbol Min Typ Max Unit VOL IC(leak) tr tf ICC http://onsemi.com 4 SG3526 V ref , REFERENCE VOLTAGE (V) −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) 150 5.0 4.0 3.0 2.0 1.0 1.0 2.0 3.0 4.0 5.0 10 20 30 40 VCC, SUPPLY VOLTAGE (V) 50 mV Spec Limit −75 −50 Figure 2. Reference Stability over Temperature Figure 3. Reference Voltage as a Function Supply Voltage 8.0 7.0 A Vol , VOLTAGE GAIN (dB) SHUTDOWN VOLTAGE (V) CComp 80 60 40 20 0 10 1 2 + _ 100 pF 3 6.0 5.0 4.0 3.0 2.0 1.0 100 1.0 k 10 k 100 k 1.0 M 10 M 0 25 50 75 100 125 150 175 200 DIFFERENTIAL INPUT VOLTAGE (mV) f, FREQUENCY (Hz) Figure 4. Error Amplifier Open Loop Frequency Response Figure 5. Current Limit Comparator Threshold 8.0 7.0 RESET VOLTAGE (V) 6.0 5.0 4.0 3.0 2.0 1.0 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 Vref, REFERENCE VOLTAGE (V) V sat , OUTPUT DRIVER SATURATION VOLTAGE (V) 2.5 2.0 1.5 1.0 0.5 0 2.0 5.0 10 20 50 100 200 OUTPUT DRIVER SINK CURRENT (mA) Figure 6. Undervoltage Lockout Characteristic Figure 7. Output Driver Saturation Voltage as a Function of Sink Current http://onsemi.com 5 SG3526 2.5 V SAT , SATURATION VOLTAGE (V) 2.0 1.5 1.0 0.5 0 2.0 200 R T, TIMING RESISTOR (k Ω ) 5.0 10 20 50 IC, SINK CURRENT (mA) 100 200 100 50 20 10 5.0 2.0 0.005 0.01 0.02 0.002 RD = 0 Ω 0.05 0.1 0.2 0.5 5.0 10 20 50 1.0 2.0 OSCILLATOR PERIOD (ms) Figure 8. VC Saturation Voltage as a Function of Sink Current VCC Figure 9. Oscillator Period Q6 Q5 125 μA Q3 50μA 50μA Q4 Vref Vref Q11 Q12 100μA 14μA Q10 Q2 3 Compensation 100μA 1.2V Bandgap Reference R1 + − R2 To Driver A To Driver B 14μA Q7 Q1 1.0k 500 Q8 100 μA Q9 1.0k 500 1 + Error − Error Figure 10. Error Amplifier Figure 11. Undervoltage Lockout Memory F/F Sync S Q PWM D Q Metering F/F PWM S R Q Clock The metering Flip−Flop is an asynchronous data latch which suppresses high frequency oscillations by allowing only one PWM pulse per oscillator cycle. The memory Flip−Flop prevents double pulsing in a push−pull configuration by remembering which output produced the last pulse. Figure 12. Pulse Processing Logic http://onsemi.com 6 100 200 500 1000 To Reset SG3526 APPLICATIONS INFORMATION Negative Output Voltage R1 Vref C* R2 27 VCC R1 17 Reference Regulator 15 Gnd * May be required with some types of transistors R3 = R1R2 R1 + R2 18 + 10μF Vout = Vref R1 + R2 R2 Vout = Vref Vref Gnd Positive Output Voltage Gnd R3 1 + 2 − R3 Vref R2 1 + 2 − R1 R2 Figure 13. Extending Reference Output Current Capability Figure 14. Error Amplifier Connections Output to Load RS 11 SG3526 12 Sync 8 RD 9 10 + 7 R2 Gnd RT CT 0.1 V + I(max) = Vout R1 R1 + R2 RS ISC = 0.1 V RS − 6 R1 Vout + − Figure 15. Oscillator Connections Figure 16. Foldback Current Limiting +12V Vref 100 μA 14 VC Ramp − PWM + Q2 SG3526 A 13 + Error − Error Reset 1 2 5 + Error − Amp Q1 Gnd B 16 Q3 To Un