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Part Number |
RMPA2263 |
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Manufacturer |
Fairchild Semiconductor |
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Semiconductor DataSheet |
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DataSheet View |
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RMPA2263
PRELIMINARY
May 2005
WCDMA Power Amplifier Module 1920–1980 MHz
Features
■ 40% WCDMA efficiency at +28 dBm Pout ■ 14% WCDMA efficiency (85 mA total current) at +16 dBm Pout ■ Linear operation in low-power mode up to +19 dBm ■ Low quiescent current (Iccq): 25 mA in low-power mode ■ Meets UMTS/WCDMA performance requirements ■ Meets HSDPA performance requirements ■ Single positive-supply operation with low power and shutdown modes – 3.4V typical Vcc operation – Low Vref (2.85V) compatible with advanced handset chipsets ■ Compact Lead-free compliant LCC package – (4.0 x 4.0 x 1.5 mm nominal) ■ Industry standard pinout ■ Internally matched to 50 Ohms and DC blocked RF input/ output
General Description
The RMPA2263 Power Amplifier Module (PAM) is Fairchild’s latest innovation in 50 Ohm matched, surface mount modules targeting UMTS/WCDMA/HSDPA applications. Answering the call for ultra-low DC power consumption and extended battery life in portable electronics, the RMPA2263 uses novel proprietary circuitry to dramatically reduce amplifier current at low to medium RF output power levels (< +16 dBm), where the handset most often operates. A simple two-state Vmode control is all that is needed to reduce operating current by more than 50% at 16 dBm output power, and quiescent current (Iccq) by as much as 70% compared to traditional power-saving methods. No additional circuitry, such as DC-to-DC converters, are required to achieve this remarkable improvement in amplifier efficiency. Further, the 4 x 4 x 1.5 mm LCC package is pin-compatible and a drop-in replacement for last generation 4 x 4 mm PAMs widely used today, minimizing the design time to apply this performance-enhancing technology. The multi-stage GaAs Microwave Monolithic Integrated Circuit (MMIC) is manufactured using Fairchild RF’s InGaP Heterojunction Bipolar Transistor (HBT) process.
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Device
Functional Block Diagram
(Top View) MMIC
Vcc1 1 RF IN GND Vmode Vref
10 Vcc2
INPUT MATCH OUTPUT MATCH BIAS/MODE SWITCH
2 3 4 5
9 GND 8 RF OUT 7 GND 6 GND
11 (paddle ground on package bottom)
©2004 Fairchild Semiconductor Corporation
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Absolute Ratings1
Symbol
Vcc1, Vcc2 Vref Vmode Pin Tstg Supply Voltages Reference Voltage Power Control Voltage RF Input Power Storage Temperature
Parameter
Ratings
5.0 2.6 to 3.5 3.5 +10 -55 to +150
Units
V V V dBm °C
Note: 1: No permanent damage with only one parameter set at extreme limit. Other parameters set to typical values.
Electrical Characteristics1
Symbol
f WCDMA Operation Gp Power Gain 27.5 23 Po Linear Output Power 28 16 PAEd PAEd (digital) @ 28dBm PAEd (digital) @ 16dBm Itot High Power Total Current Low Power Total Current Adjacent Channel Leakage Ratio ACLR1 ±5.00MHz Offset -40 -46 ACLR2 ±10.0MHz Offset -52 -57 General Characteristics VSWR NF Rx No 2fo 3fo–5fo S Input Impedance Noise Figure Receive Band Noise Power Harmonic Suppression Harmonic Suppression Spurious Outputs
2, 3
Parameter
Operating Frequency
Min
1920
Typ
Max
1980
Units
MHz
Comments
dB dB dBm dBm
Po=+28dBm, Vmode=0V Po=+16dBm, Vmode≥2.0V Vmode=0V Vmode≥2.0V Vmode=0V Vmode≥2.0V Po=+28dBm, Vmode=0V Po=+16dBm, Vmode≥2.0V WCDMA Modulation 3GPP 3.2 03-00 DPCCH+1 DCDCH
40 13 460 85
% % mA mA
dBc dBc dBc dBc
Po=+28dBm, Vmode=0V Po=+16dBm, Vmode≥2.0V Po=+28dBm, Vmode=0V Po=+16dBm, Vmode≥2.0V
2.0:1 4 -139 -38 -55
2.5:1 dB dBm/Hz Po≤+28dBm, 2110 to 2170 MHz dBc dBc -60 10:1 dBc Po≤+28dBm Po≤+28dBm Load VSWR≤5.0:1 No permanent damage °C
Ruggedness with Load Mismatch3 Tc Case Operating Temperature -30
85
DC Characteristics Iccq Iref Icc(off) Quiescent Current Reference Current Shutdown Leakage Current 25 7 1 5 mA mA µA Vmode≥2.0V Po≤+28dBm No applied RF signal
Notes: 1. All parameters met at Tc = +25°C, Vcc = +3.4V, Vref = 2.85V and load VSWR ≤ 1.2:1, unless otherwise noted. 2. All phase angles. 3. Guaranteed by design.
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Recommended Operating Conditions
Symbol
f Vcc1, Vcc2 Vref Supply Voltage Reference Voltage Operating Shutdown Bias Control Voltage Low-Power High-Power Linear Output Power High-Power Low-Power Case Operating Temperature -30
Parameter
Operating Frequency
Min
1920 3.0 2.7 0 1.8 0
Typ
3.4 2.85
Max
1980 4.2 3.1 0.5 3.0 0.5 +28 +19 +85
Units
MHz V V V V V dBm dBm °C
Vmode
2.0
Pout
+16
Tc
DC Turn On Sequence:
1. Vcc1 = Vcc2 = 3.4V (typical) 2. Vref = 2.85V (typical) 3. High-Power: Vmode = 0V (Pout > 16dBm) Low-Power: Vmode = 2.0V (Pout < 16dBm)
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Evaluation Board Layout
1 5 3 6 6 5
2
4
7 5
Materials List
Qty
1 2 5 Ref 3 3 2 1 1 A/R A/R
Item No.
1 2 3 4 5 5 (Alt) 6 7 7 (Alt) 8 9
Part Number
G657553-1 V2 #142-0701-841 #2340-5211TN GRM39X7R102K50V ECJ-1VB1H102K C3216X5R1A335M GRM39Y5V104Z16V ECJ-1VB1C104K SN63 SN96 PC Board
Description
SMA Connector Terminals Assembly, RMPA2263 1000pF Capacitor (0603) 1000pF Capacitor (0603) 3.3µF Capacitor (1206) 0.1µF Capacitor (0603) 0.1µF Capacitor (0603) Solder Paste Solder Paste
Vendor
Fairchild Johnson 3M Fairchild Murata Panasonic TDK Murata Panasonic Indium Corp. Indium Corp.
Evaluation Board Schematic
3.3 µF VCC1 SMA1 RF IN VMODE VREF 1000 pF 0.1 µF 50 Ohm TRL 4 5 11 (PACKAGE BASE) 1000 pF 1 2 10 1000 pF 3.3 µF VCC2 50 Ohm TRL SMA2 RF OUT
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3, 6, 7, 9
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Package Outline
I/O 1 INDICATOR TOP VIEW 1 2 10 9
(4.00mm +.100 ) SQUARE –.050
3 4 5
8
6
1.60mm MAX.
FRONT VIEW .25mm TYP. 3.50mm TYP. See Detail A .40mm .30mm TYP. .85mm TYP. 11 2 1 1.08mm 1.84mm BOTTOM VIEW .18mm DETAIL A. TYP. 3.65mm .10mm .10mm .40mm .45mm
Signal Descriptions
Pin #
1 2 3 4 5 6 7 8 9 10 11
Signal Name
Vcc1 RF In GND Vmode Vref GND GND RF Out GND Vcc2 GND
Description
Supply Voltage to Input Stage RF Input Signal Ground High Power/Low Power Mode Control Reference Voltage Ground Ground RF Output Signal Ground Supply Voltage to Output Stage Paddle Ground
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WCDMA Power Amplifier Module 1920–1980 MHz (Preliminary)
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Applications Information
CAUTION: THIS IS AN ESD SENSITIVE DEVICE. Precautions to Avoid Permanent Device Damage: • Cleanliness: Observe proper handling procedures to ensure clean devices and PCBs. Devices should remain in their original packaging until component placement to ensure no contamination or damage to RF, DC and ground contact areas. • Device Cleaning: Standard board cleaning techniques should not present device problems provided that the boards are properly dried to remove solvents or water residues. • Static Sensitivity: Follow ESD precautions to protect against ESD damage: – A properly grounded static-dissipative surface on which to place devices. – Static-dissipative floor or mat. – A properly grounded conductive wrist strap for each person to wear while handling devices. • General Handling: Handle the package on the top with a vacuum collet or along the edges with a sharp pair of bent tweezers. Avoiding damaging the RF, DC, and ground contacts on the package bottom. Do not apply excessive pressure to the top of the lid. • Device Storage: Devices are supplied in heat-sealed, moisture-barrier bags. In this condition, devices are protected and require no special storage conditions. Once the sealed bag has been opened, devices should be stored in a dry nitrogen environment. Device Usage: Fairchild recommends the following procedures prior to assembly. • Assemble the devices within 7 days of removal from the dry pack. • During the 7-day period, the devices must be stored in an environment of less than 60% relative humidity and a maximum temperature of 30°C • If the 7-day period or the environmental conditions have been exceeded, then the dry-bake procedure, at 125°C for 24 hours minimum, must be performed. Solder Materials & Temperature Profile: Reflow soldering is the preferred method of SMT attachment. Hand soldering is not recommended. Reflow Profile • Ramp-up: During this stage the solvents are evaporated from the solder paste. Care should be taken to prevent rapid oxidation (or paste slump) and solder bursts caused by violent solvent out-gassing. A maximum heating rate is 3°C/sec. • Pre-heat/soak: The soak temperature stage serves two purposes; the flux is activated and the board and devices achieve a uniform temperature. The recommended soak condition is: 60-180 seconds at 150-200°C. • Reflow Zone: If the temperature is too high, then devices may be damaged by mechanical stress due to thermal mismatch or there may be problems due to excessive solder oxidation. Excessive time at temperature can enhance the formation of inter-metallic compounds at the lead/board interface and may lead to early mechanical failure of the joint. Reflow must occur prior to the flux being completely driven off. The duration of peak reflow temperature should not exceed 20 seconds. Soldering temperatures should be in the range 255–260°C, with a maximum limit of 260°C. • Cooling Zone: Steep thermal gradients may give rise to excessive thermal shock. However, rapid cooling promotes a finer grain structure and a more crack-resistant solder joint. The illustration below indicates the recommended soldering profile. Solder Joint Characteristics: Proper operation of this device depends on a reliable void-free attachment of the heat sink to the PWB. The solder joint should be 95% void-f |