FSK Demodulator/Tone Decoder
¥ Wide frequency range Ð 0.01 Hz to 300 kHz
¥ Wide supply voltage range Ð 4.5V to 20V
¥ DTL/TTL/ECL logic compatibility
¥ FSK demodulation with carrier-detector
¥ Wide dynamic range Ð 2 mV to 3 VRMS
¥ Adjustable tracking range Ð ±1% to ±80%
¥ Excellent temperature stability Ð 20 ppm/°C typical
¥ FSK demodulation
¥ Data synchronization
¥ Tone decoding
¥ FM detection
¥ Carrier detection
The RC2211 is a monolithic phase-locked loop (PLL)
system especially designed for data communications. It is
particularly well-suited for FSK modem applications, and
operates over a wide frequency range of 0.01 Hz to 300 kHz.
It can accommodate analog signals between 2 mV and 3V,
and can interface with conventional DTL, TTL and ECL
logic families. The circuit consists of a basic PLL for
tracking an input signal frequency within the passband, a
quadrature phase detector which provides carrier detection,
and an FSK voltage comparator which provides FSK
demodulation. External components are used to indepen-
dently set carrier frequency, bandwidth and output delay.
This document was created with FrameMaker 4 0 4
Description of Circuit Controls
Signal Input (Pin 2)
The input signal is AC coupled to this terminal. The internal
impedance at pin 2 is 20 kW. Recommended input signal
level is in the range of 10 mVRMS to 3 VRMS.
Quadrature Phase Detector Output, Q (Pin 3)
This is the high impedance output of the quadrature phase
detector, and is internally connected to the input of lock
detector voltage comparator. In tone detection applications,
pin 3 is connected to ground through a parallel combination
of RD and CD (see Figure 1) to eliminate chatter at the lock
detector outputs. If this tone detector section is not used,
pin 3 can be left open circuited.
Lock Detector Output, Q (Pin 5)
The output at pin 5 is at a ÒhighÓ state when the PLL is out of
lock and goes to a ÒlowÓ or conducting state when the PLL is
locked. It is an open collector output and requires a pull-up
resistor, RL, to +VS for proper operation. In the ÒlowÓ state it
can sink up to 5 mA of load current.
Lock Detector Complement, Q (Pin 6)
The output at pin 6 is the logic complement of the lock
detector output at pin 5. This output is also an open collector
type stage which can sink 5 mA of load current in the low or
FSK Data Output (Pin 7)
This output is an open collector stage which requires a
pull-up resistor, RL, to +VS for proper operation. It can sink
5 mA of load current. When decoding FSK signals the FSK
data output will switch to a ÒhighÓ or off state for low input
frequency, and will switch to a ÒlowÓ or on state for high
input frequency. If no input signal is present, the logic state
at pin 7 is indeterminate.
FSK Comparator Input (Pin 8)
This is the high impedance input to the FSK voltage
comparator. Normally, an FSK post detection or data Þlter is
connected between this terminal and the PLL phase detector
output (pin 11). This data Þlter is formed by RF and CF of
Figure 1. The threshold voltage of the comparator is set by
the internal reference voltage, VR, available at pin 10.
Reference Bypass (Pin 9)
This pin can have an optional 0.1, mF capacitor connected to
Reference Voltage, VR (Pin 10)
This pin is internally biased at the reference voltage level,
VR; VR = +VS/2 Ð 650 mV. The DC voltage level at this pin
forms an internal reference for the voltage levels at pin 3, 8,
11 and 12. Pin 10 must be bypassed to ground with a 0.1 mF
(12) (10) Internal
(13) R0 0.1 µF
Figure 1. Generalized Circuit Connection for FSK and Tone Detection
Loop Phase Detector Output (Pin 11)
This terminal provides a high impedance output for the loop
phase detector. The PLL loop Þlter is formed by R1 and C1
connected to pin 11 (see Figure 1). With no input signal, or
with no phase error within the PLL, the DC level at pin 11 is
very nearly equal to VR. The peak voltage swing available at
the phase detector output is equal to ±VR.
VCO Control Input (Pin 12)
VCO free running frequency is determined by external
timing resistor, R0, connected from this terminal to ground.
The VCO free running frequency, F0 is given by:
where C0 is the timing capacitor across pins 13 and 14. For
optimum temperature stability R0 must be in the range of
10 kW to 100 kW (see Typical Performance Characteristics).
This terminal is a low impedance point, and is internally
biased at a DC level equal to VR. The maximum timing cur-
rent drawn from pin 12 must be limited to £3 mA for proper
operation of the circuit.
VCO Timing Capacitor (Pins 13 and 14)
VCO frequency is inversely proportional to the external tim-
ing capacitor, C0, connected across these terminals. C0 must
be non-polarized, and in the range of 200 pF to 10 mF.
VCO Frequency Adjustment
VCO can be Þne tuned by connecting a potentiometer, Rx, in
series with R0 at pin 12 (see Figure 2).
VCO Free-Running Frequency, F0
The RC2211 does not have a separate VCO output terminal.
Instead, the VCO outputs are internally connected to the
phase detector sections of the circuit. However, for set-up or
adjustment purposes, the VCO freerunning frequency can be
measured at pin 3 (with CD disconnected) with no input and
with pin 2 shorted to pin 10.
See Figure 1 for DeÞnitions of Components.
1. VCO Center Frequency, F0:
2. Internal Reference Voltage, VR (measured at pin 10)
3. Loop Lowpass Filter Time Constant, t
t = R1C1
4. Loop Dampening, z:
5. Loop Tracking Bandwidth, ±DF/F0:
Df/FO = R0/R1
F0 F2 FLH
6. FSK Data Filter Time Constant, tF:
tF = RFCF
7. Loop Phase Detector Conversion Gain, Kf (Kf is the
differential DC voltage across pins 10 and 11, per unit
of phase error at phase-detector input):
kf (in volts per radian) = -(---Ð---2----)--p--(--V-----R---)--
8. VCO Conversion Gain, K0 is the amount of change in
VCO frequency per unit of DC voltage change at pin 11:
K0 (in Hertz per volt)
9. Total Loop Gain, KT:
KT (in radians per second per volt)= 2 pKfK0
10. Peak Phase Detector Current, IA:
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