®
PX3511D
Data Sheet February 26, 2007 FN6463.0
Advanced Synchronous Rectified Buck MOSFET Driver with Protection Features
The PX3511D is high frequency MOSFET driver specifically designed to drive upper and lower power N-Channel MOSFETs in a synchronous rectified buck converter topology. This driver combined with the PX3511D Digital Multi-Phase Buck PWM controller and N-Channel MOSFETs forms a complete core-voltage regulator solution for advanced microprocessors. The PX3511D drives both upper and lower gates over a range of 4.5V to 13.2V. This drive-voltage provides the flexibility necessary to optimize applications involving tradeoffs between gate charge and conduction losses. An advanced adaptive zero shoot-through protection is integrated to prevent both the upper and lower MOSFETs from conducting simultaneously and to minimize the dead time. The PX3511D includes an overvoltage protection feature operational before VCC exceeds its turn-on threshold, at which the PHASE node is connected to the gate of the low side MOSFET (LGATE). The output voltage of the converter is then limited by the threshold of the low side MOSFET, which provides some protection to the microprocessor if the upper MOSFET(s) is shorted. The PX3511D also features an input that recognizes a highimpedance state, working together with Intersil multi-phase PWM controllers to prevent negative transients on the controlled output voltage when operation is suspended. This feature eliminates the need for the schottky diode that may be utilized in a power system to protect the load from negative output voltage damage.
Features
• Dual MOSFET Drives for Synchronous Rectified Bridge • Pin-to-pin Compatible with ISL6596 • Advanced Adaptive Zero Shoot-Through Protection - Body Diode Detection - Auto-zero of rDS(ON) Conduction Offset Effect • Adjustable Gate Voltage for Optimal Efficiency • 36V Internal Bootstrap Schottky Diode • Bootstrap Capacitor Overcharging Prevention • Supports High Switching Frequency (up to 2MHz) - 3A Sinking Current Capability - Fast Rise/Fall Times and Low Propagation Delays • Optimized for 3.3V PWM Input • Three-State PWM Input for Output Stage Shutdown • Three-State PWM Input Hysteresis for Applications With Power Sequencing Requirement • Pre-POR Overvoltage Protection • VCC Undervoltage Protection • Expandable Bottom Copper Pad for Enhanced Heat Sinking • Dual Flat No-Lead (DFN) Package - Near Chip-Scale Package Footprint; Improves PCB Efficiency and Thinner in Profile • Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Optimized for POL DC/DC Converters for IBA Systems • Core Regulators for Intel® and AMD® Microprocessors
Ordering Information
PART NUMBER PART (Note) MARKING PX3511DDDG-RA 11DD TEMP. RANGE (°C) PACKAGE (Pb-free) PKG. DWG. #
• High Current DC/DC Converters • High Frequency and High Efficiency VRM and VRD
0 to +85 10 Ld 3x3 DFN L10.3X3 Tape and Reel
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Related Literature
Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” Technical Brief TB389 “PCB Land Pattern Design and Surface Mount Guidelines for QFN (MLFP) Packages”
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
PX3511D Pinouts
PX3511D (10 LD 3x3 DFN) TOP VIEW
UGATE BOOT N/C PWM GND 1 2 3 4 5 GND 10 PHASE 9 PVCC 8 7 N/C VCC 6 LGATE
Block Diagram
PX3511D
UVCC VCC +5V 13.6K PWM POR/ CONTROL 6.4K LOGIC Pre-POR OVP FEATURES
BOOT UGATE PHASE (LVCC) PVCC UVCC = PVCC FOR PX3511D
SHOOTTHROUGH PROTECTION
LGATE
GND PAD FOR DFN DEVICES, THE PAD ON THE BOTTOM SIDE OF THE PACKAGE MUST BE SOLDERED TO THE CIRCUIT’S GROUND.
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FN6463.0 February 26, 2007
Typical Application - 4 Channel Converter Using ISL6595 and PX3511D Gate Drivers
+12V
PX3511D +5V 1 UGATE 2 BOOT 3 PWM 4 GND PHASE 8 PVCC 7 VCC 6 LGATE 5
3
+3.3V VDD V12_SEN GND PX3511D 1 UGATE 2 BOOT 3 PWM 4 GND PHASE 8 PVCC 7 VCC 6 LGATE 5
ISL6595
VID4 VID3 VID2 VID1 FROM µP VID0 VID5 LL0 LL1 OUTEN
OUT1 OUT2 ISEN1 OUT3
PX3511D
OUT4 ISEN2 OUT5 OUT6 ISEN3 OUT7 OUT8 PX3511D 1 UGATE 2 BOOT 3 PWM 4 GND PHASE 8 PVCC 7 VCC 6 LGATE 5 RTN Vout
TO µP
VCC_PWRGD
ISEN4 OUT9
RESET_N
OUT10 ISEN5
PX3511D 1 UGATE 2 BOOT 3 PWM 4 GND PHASE 8 PVCC 7 VCC 6 LGATE 5
FAULT OUTPUTS
FAULT1 FAULT2
OUT11 OUT12 ISEN6
SDA I2C I/F BUS SCL SADDR
FN6463.0 February 26, 2007
TEMP_SEN RTHERM CAL_CUR_EN CAL_CUR_SEN VSENP VSENN
PX3511D
Absolute Maximum Ratings
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V BOOT Voltage (VBOOT-GND). . . . . . . . . . . . . . . . . . . . . . . . . . . .36V Input Voltage (VPWM) . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 7V UGATE. . . . . . . . . . . . . . . . . . . VPHASE - 0.3VDC to VBOOT + 0.3V VPHASE - 3.5V (<100ns Pulse Width, 2µJ) to VBOOT + 0.3V LGATE . . . . . . . . . . . . . . . . . . . . . . GND - 0.3VDC to VPVCC + 0.3V GND - 5V (<100ns Pulse Width, 2µJ) to VPVCC + 0.3V PHASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3VDC to 15VDC GND - 8V (<400ns, 20µJ) to 30V (<200ns, VBOOT-GND<36V)) ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . Class I JEDEC STD
Thermal Information
Thermal Resistance θJA (°C/W) θJC (°C/W) SOIC Package (Note 1) . . . . . . . . . . . . 100 N/A DFN Package (Notes 2, 3) . . . . . . . . . . 48 7 Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C (SOIC - Lead Tips Only)
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . 0°C to +85°C Maximum Operating Junction Temperature . . . . . . . . . . . . . +125°C Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8V to 13.2V Supply Voltage Range, PVCC . . . . . . . . . . . . . . . . 5V to 12V ±10%
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. 2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 3. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER VCC SUPPLY CURRENT Bias Supply Current
Recommended Operating Conditions, Unless Otherwise Noted. SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
IVCC IVCC
PX3511D, fPWM = 300kHz, VVCC = 12V PX3511D, fPWM = 1MHz, VVCC = 12V PX3511D, fPWM = 300kHz, VPVCC = 12V PX3511D, fPWM = 1MHz, VPVCC = 12V
-
4.5 5 7.5 8.5
-
mA mA mA mA
Gate Drive Bias Current
IPVCC IPVCC
POWER-ON RESET AND ENABLE VCC Rising Threshold VCC Falling Threshold PWM INPUT (See Timing Diagram on Page 6) Input Current IPWM VPWM = 3.3V VPWM = 0V PWM Rising Threshold (Note 4) PWM Falling Threshold (Note 4) Typical Three-State Shutdown Window Three-State Lower Gate Falling Threshold Three-State Lower Gate Rising Threshold Three-State Upper Gate Rising Threshold Three-State Upper Gate Falling Threshold Shutdown Holdoff Time UGATE Rise Time (Note 4) LGATE Rise Time (Note 4) tTSSHD tRU tRL VPVCC = 12V, 3nF Load, 10% to 90% VPVCC = 12V, 3nF Load, 10% to 90% VCC = 12V VCC = 12V VCC = 12V VCC = 12V VCC = 12V VCC = 12V VCC = 12V 1.23 400 -350 1.70 1.30 1.18 0.76 2.36 1.96 245 26 18 1.82 µA µA V V V V V V V ns ns ns 6.1 4.7 6.4 5.0 6.7 5.3 V V
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FN6463.0 February 26, 2007
PX3511D
Electrical Specifications
PARAMETER UGATE Fall Time (Note 4) LGATE Fall Time (Note 4) UGATE Turn-On Propagation Delay (Note 4) LGATE Turn-On Propagation Delay (Note 4) UGATE Turn-Off Propagation Delay (Note 4) LGATE Turn-Off Propagation Delay (Note 4) LG/UG Three-State Propagation Delay (Note 4) OUTPUT (Note 4) Upper Drive Source Current Upper Drive Source Impedance Upper Drive Sink Current Upper Drive Sink Impedance Lower Drive Source Current Lower Drive Source Impedance Lower Drive Sink Current Lower Drive Sink Impedance NOTE: 4. Guaranteed by Characterization. Not 100% tested in production. IU_SOURCE VPVCC = 12V, 3nF Load RU_SOURCE 150mA Source Current IU_SINK RU_SINK IL_SOURCE VPVCC = 12V, 3nF Load 150mA Sink Current VPVCC = 12V, 3nF Load 1.4 0.9 0.85 0.60 1.25 2.0 2 1.65 2 1.3 3 0.94 3.0 3.0 2.2 1.35 A Ω A Ω A Ω A Ω Recommended Operating Conditions, Unless Otherwise Noted. (Continued) SYMBOL tFU tFL tPDHU tPDHL tPDLU tPDLL tPDTS TEST CONDITIONS VPVCC = 12V, 3nF Load, 90% to 10% VPVCC = 12V, 3nF Load, 90% to 10% VPVCC = 12V, 3nF Load, Adaptive VPVCC = 12V, 3nF Load, Adaptive VPVCC = 12V, 3nF Load VPVCC = 12V, 3nF Load VPVCC = 12V, 3nF Load MIN TYP 18 12 10 10 10 10 10 MAX UNITS ns ns ns ns ns ns ns
RL_SOURCE 150mA Source Current IL_SINK RL_SINK VPVCC = 12V, 3nF Load 150mA Sink Current
Functional Pin Description
PACKAGE PIN # SOIC 1 2 DFN 1 2 PIN
