TRANSFER-MOLD TYPE INSULATED TYPE

www.DataSheet4U.com MITSUBISHI SEMICONDUCTOR MITSUBISHI SEMICONDUCTOR PS21343-N PS21343-N TRANSFER-MOLD TYPE TRANSFER-MOLD TYPE INSULATED TYPE INSULATED TYPE PS21343-N INTEGRATED POWER FUNCTIONS 600V/10A low-loss 4th generation (planar) IGBT inverter bridge for 3 phase DC-to-AC power conversion. INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS • For upper-leg IGBTS : Drive circuit, High voltage isolated high-speed level shifting, Control circuit under-voltage (UV) protection. Note : Bootstrap supply scheme can be applied. • For lower-leg IGBTS : Drive circuit, Control circuit under-voltage protection (UV), Short-circuit protection (SC). • Fault signaling : Corresponding to a SC fault (Low-side IGBT) or a UV fault (Low-side IGBT). • Input interface : 5V line CMOS/TTL compatible, Schmitt Trigger receiver circuit. APPLICATION AC100V~200V inverter drive for motor control. Fig. 1 PACKAGE OUTLINES HEAT SINK SIDE (3.556) (1) TERMINAL (0.5) (3.556) (1.656) (0.5) Dimensions in mm TERMINAL CODE VUFS (UPG) VUFB VP1 (COM) UP VVFS (VPG) VVFB VP1 (COM) VP VWFS (WPG) VWFB VP1 (COM) WP (UNG) VNO(NC) UN VN WN FO CFO CIN VNC VN1 (WNG) (VNG) P U V W N (1) (0.5) DUMMY PIN (1.778 × 26) (1.778) (6.25) (6.25) (6.25) (8) (8) A (0.5) (30.5) (0.75) 29 30 Type name , Lot No. (φ3 .3) (17.4) (17.4) 28 27 26 25 24 23 22 21 20 19 18 16 17 15 13 14 12 10 11 987 654 321 D (φ2 EP TH 2) 35 34 33 32 31 (7.62 × 4) (41) (42) (49) (0.5) (7.62) (4MIN) 1 2 3 4 5 PCB 6 (1) PATTERN 7 8 (1.9) SLIT 9 (1.8MIN) 10 (PCB LAYOUT) 11 Detail A *Note2 12 13 (5) 14 15 16 17 18 19 20 21 22 23 HEAT SINK SIDE 24 (35 °) 25 26 27 28 29 30 31 32 33 (1.25) 34 (2.5) 35 (6.5) (10.5) (1.5) (1.2) *Note1:(***) = Dummy Pin. *Note 2: In order to increase the surface distance between terminals, cut a slit, etc. on the PCB surface when mounting a module. Sep. 2001 MITSUBISHI SEMICONDUCTOR PS21343-N TRANSFER-MOLD TYPE INSULATED TYPE Fig. 2 INTERNAL FUNCTIONS BLOCK DIAGRAM (TYPICAL APPLICATION EXAMPLE) CBW+ CBW– CBV+ CBV– CBU– CBU+ C3 : Tight tolerance, temp-compensated electrolytic type (Note : The capacitance value depends on the PWM control scheme used in the applied system). C4 : 0.22~2µF R-category ceramic capacitor for noise filtering. High-side input (PWM) (5V line) (Note 1,2) Input signal Input signal Input signal coditioning coditioning coditioning Level shifter Level shifter Level shifter Protection circuit (UV) C4 C3 Protection circuit (UV) Protection circuit (UV) (Note 6) DIP-IPM Inrush current limiter circuit Drive circuit Drive circuit Drive circuit P H-side IGBTS AC input (Note 4) C Z U V W M AC line output Fig. 3 N1 VNC N CIN Drive circuit L-side IGBTS Z : ZNR (Surge absorber) C : AC filter (Ceramic capacitor 2.2~6.5nF) (Note : Additionally, an appropriate line to line surge absorber circuit may become necessary depending on the application environment.) Input signal conditioning Fo logic SC protection Control supply Under-Voltage protection FO CFO Low-side input (PWM) (5V line) (Note 1, 2) FO output (5V line) (Note 3, 5) Note1: 2: 3: 4: 5: 6: To prevent the input signals oscillation, an RC coupling at each input is recommended. (see also Fig. 6) By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU terminals without any opto-coupler or transformer isolation is possible. (see also Fig. 6) This output is open collector type. The signal line should be pulled up to the positive side of the 5V power supply with approximately 5.1kΩ resistance. (see also Fig. 6) The wiring between the power DC link capacitor and the P/N1 terminals should be as short as possible to protect the DIP-IPM against catastrophic high surge voltages. For extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to these P and N1 DC power input terminals. tFO=1.8ms (Typ.)) Fo output pulse width should be decided by connecting external capacitor between CFO and VNC terminals. (Example : CFO=22nF High voltage (600V or more) and fast recovery type (less than 100ns) diodes should be used in the bootstrap circuit. VNC VD (15V line) Fig. 3 EXTERNAL PART OF THE DIP-IPM PROTECTION CIRCUIT DIP-IPM Drive circuit P Short Circuit Protective Function (SC) : SC protection is achieved by sensing the L-side DC-Bus current (through the external shunt resistor) after allowing a suitable filtering time (defined by the RC circuit). When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is recommended to stop the system when the Fo signal is received and check the fault. IC (A) SC Protection Trip Level H-side IGBTS U V W L-side IGBTS External protection circuit N1 Shunt Resistor (Note 1) A N VNC CIN B Drive circuit Collector current waveform C R C Protection circuit (Note 2) 0 2 tw (µs) Note1: In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0µs. 2: To prevent erroneous protection operation, the wiring of A, B, C should be as short as possible. Sep. 2001 MITSUBISHI SEMICONDUCTOR PS21343-N TRANSFER-MOLD TYPE INSULATED TYPE MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted) INVERTER PART Symbol VCC VCC(surge) VCES ±IC ±ICP PC Tj Parameter Supply voltage Supply voltage (surge) Collector-emitter voltage Each IGBT collector current Each IGBT collector current (peak) Collector dissipation Junction temperature Condition Applied between P-N Applied between P-N Tf = 25°C Tf = 25°C, instantaneous value (pulse) Tf = 25°C, per 1 chip (Note 1) Ratings 450 500 600 10 20 25 –20~+150 Unit V V V A A W °C Note 1 : The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150°C (@ Tf ≤ 100°C). However, to ensure safe operation of the DIP-IPM, the average junction temperature should be limited to T j(ave) ≤ 125°C (@ Tf ≤ 100°C). CONTROL (PROTECTION) PART Symbol VD VDB VCIN VFO IFO VSC Parameter Control supply voltage Control supply voltage Input voltage Fault output supply voltage Fault output current Current sensing input voltage Condition Applied between VP1-VNC , VN1 -VNC Applied between VUFB -VUFS, VVFB-V VFS, VWFB-VWFS Applied between UP, VP, WP-VNC, UN, VN, WN-VNC Applied between FO-VNC Sink current at F O terminal Applied between CIN-V NC Ratings 20 20 –0.5~VD+0.5 –0.5~VD+0.5 15 –0.5~VD+0.5 Unit V V V V mA V TOTAL SYSTEM Symbol Parameter VCC(PROT) Self protection supply voltage limit (short-circuit protection capability) Heat-fin operation temperature Tf Tstg Viso Storage temperature Isolation voltage 60Hz, Sinusoidal, 1 minute, connection pins to heat-sink plate Condition VD = VDB = 13.5~16.5V, Inverter part Tj = 125°C, non-repetitive, less than 2 µs (Note 2) Ratings 400 –20~+100 –40~+125 1500 Unit V °C °C Vrms Note 2 : Tf MEASUREMENT POINT Al Board Specifications: Dimensions 100 × 100 × 10mm, finishing: 12s, warp: –50~100µm Control Terminals FWD Chip 18mm 16mm Al Board IGBT/FWD Chip Groove IGBT Chip Temp. measurement point (inside the Al board) N W V U P Temp. measurement point (inside the Al board) Power Terminals 100~200µm of evenly applied Silicon-Grease Sep. 2001 MITSUBISHI SEMICONDUCTOR PS21343-N TRANSFER-MOLD TYPE INSULATED TYPE THERMAL RESISTANCE Symbol Rth(j-f)Q Rth(j-f)F Parameter Junction-to-heat sink thermal resistance Condition Inverter IGBT part (per 1/6 module) Inverter FWD part (per 1/6 module) (Note 3) (Note 3) Min. — — Limits Typ. — — Max. 5.0 6.5 Unit °C/W °C/W Note 3 : Grease with good thermal conductivity should be applied evenly about +100µm~+200µm on the contact surface of a DIP-IPM and a heat sink. ELECTRICAL CHARACTERISTICS (Tj = 25°C, unless otherwise noted) INVERTER PART Symbol VCE(sat) VEC ton trr tc(on) toff tc(off) ICES Parameter Collector-emitter saturation voltage FWD forward voltage Condition IC = 10A, Tj = 25°C VD = VDB = 15V VCIN = 0V IC = 10A, Tj = 125°C Tj = 25°C, –IC = 10A, VCIN = 5V VCC = 300V, V D = V DB =15V IC = 10A, Tj = 125°C Switching times Inductive load (upper-lower arm) VCIN = 5 ↔ 0V VCE = VCES Tj = 25°C Tj = 125°C Min. — — — 0.40 — — — — — — Limits Typ. 1.55 1.65 2.1 0.90 0.20 0.40 1.2 0.6 — — Max. 2.15 2.25 2.85 1.35 — 0.65 1.65 1.3 1 10 Unit V V µs µs µs µs µs mA Collector-emitter cut-off current CONTROL (PROTECTION) PART Symbol Parameter VD = VDB =15V VCIN = 5V Condition Total of VP1-VNC, VN1 -VNC VUFB-VUFS, V VFB-VVFS, V WFB-VWFS Total of VP1-VNC, VN1 -VNC VD = VDB =15V VUFB-VUFS, V VFB-VVFS, V WFB-VWFS VCIN = 0V VSC = 0V, FO = 10kΩ 5V pull-up VSC = 0V, IFO = 1.5mA VSC = 1V, IFO = 15mA (Note 4) Tj = 25°C, VD = 15V Trip level Reset level T j ≤ 125°C Trip level Reset level Min. — — — — 4.9 — 0.8 0.43 10.0 10.5 10.3 10.8 1.0 0.8 2.5 Limits Typ. — — — — — 0.6 1.2 0.48 — — — — 1.8 1.4 3.0 Max. 8.5 1.0 9.7 1.0 — 0.9 1.8 0.53 12.0 12.5 12.5 13.0 — 2.0 4.0 Unit mA mA ID Circuit current V V V Short-circuit trip level V V V Supply circuit under-voltage protection V V ms Fault output pulse width CFO = 22nF (Note 5) ON threshold voltage V Applied between: OFF threshold voltage V UP, VP, WP-VNC, UN, VN, WN-VNC Note 4 : Short-circuit protection operates only at the low-arms. Please select the value of the external shunt resistor such that the SC trip level is less than 17A 5 : Fault signal is outputted when the low-arm short-circuit or control supply under-voltage protective functions operate. The fault output pulse-width tFO depends on the capacitance value of CFO according to the following approximate equation. : CFO = (12.2 ✕ 10-6) ✕ tFO [F] Fault output voltage