Zero standby power CMOS versatile PAL devices

www.DataSheet4U.com INTEGRATED CIRCUITS PLC18V8Z Zero standby power CMOS versatile PAL devices Product specification Replaces data sheet PLC18V8Z35/PLC18V8ZI of Dec 19 1995, and data sheet PLC18V8Z25/PLC18V8ZI of Dec 19, 1995 1997 Aug 08 Philips Semiconductors www.DataSheet4U.com Philips Semiconductors Product specification Zero standby power CMOS versatile PAL devices • Industrial control • Medical Instruments • Portable communications equipment PIN CONFIGURATIONS PLC18V8Z DESCRIPTION The PLC18V8Z is a universal PAL® device featuring high performance and virtually zero-standby power for power sensitive applications. They are reliable, user-configurable substitutes for discrete TTL/CMOS logic. While compatible with TTL and HCT logic, the PLC18V8Z can also replace HC logic over the VCC range of 4.5 to 5.5V. The PLC18V8Z is a two-level logic element comprised of 10 inputs, 74 AND gates (product terms) and 8 output Macro cells. Each output features an “Output Macro Cell” which can be individually configured as a dedicated input, a combinatorial output, or a registered output with internal feedback. As a result, the PLC18V8Z is capable of emulating all common 20-pin PAL devices to reduce documentation, inventory, and manufacturing costs. A power-up reset function and a Register Preload function have been incorporated in the PLC18V8Z architecture to facilitate state machine design and testing. With a standby current of less than 100µA and active power consumption of 1.5mA/MHz, the PLC18V8Z is ideally suited for power sensitive applications in battery operated/backed portable instruments and computers. The PLC18V8Z is also processed to industrial requirements for operation over an extended temperature range of -40°C to +85°C and supply voltage of 4.5V to 5.5V. Ordering information can be found on the following page. D, DB, DH, N, Packages I0/CLK I1 I2 I3 I4 I5 I6 I7 I8 1 2 3 4 5 6 7 8 9 20 VCC 19 F7 18 F6 17 F5 16 F4 15 F3 14 F2 13 F1 12 F0 11 I9/OE GND 10 D = Plasitc Small Outline Large Package (300mil-wide) DB = Plastic Shrink Small Outline Package (5.3mm wide) DH = Plastic Thin Shrink Small Outline Package (4.4mm wide) N = Plastic Dual In-Line Package (DIP) (300mil-wide) A Package I2 I0/ I1 CLK VCC F7 2 1 20 19 18 F6 17 F5 16 F4 15 F3 14 F2 9 10 11 12 13 FEATURES 3 I3 I4 I5 I6 I7 4 5 6 7 8 • 20-pin Universal Programmable Array Logic • Virtually Zero-Standby-power – 20µA (typical) • Available in DIP, PLCC, SOL (Small Outline), SSOP (Shrink Small Outline), and TSSOP (Thin Shrink Small Outline) packages • Functional replacement for Series 20 PAL devices • Up to 18 inputs and 8 input/output macro cells • Programmable output polarity • Power-up reset on all registers • Register Preload capability • Synchronous Preset/Asynchronous Reset • Security fuse to prevent duplication of proprietary designs • Also available in 3V operation–the P3C18V8Z APPLICATIONS – IOL = 24mA I8 GND I9/ F0 F1 OE A = Plastic Leaded Chip Carrier SP00544 PIN DESCRIPTIONS I B O D F CLK OE Dedicated Input Bidirectional input/output Dedicated output Registered output (D-type flip-flop) Output/Input Macrocell Clock Input Output Enable Supply Voltage Ground • Battery powered instruments • Laptop and pocket computers VCC GND PAL is a registered trademark of Advanced Micro Devices, Inc. 1997 Aug 08 2 853–2016 18258 www.DataSheet4U.com Philips Semiconductors Product specification Zero standby power CMOS versatile PAL devices PLC18V8Z ORDERING INFORMATION DESCRIPTION 20-Pin (300mil-wide) Plastic Dual In-Line Package, 25ns tPD 20-Pin (350mil square) Plastic Leaded Chip Carrier Package 20-Pin (300mil-wide) Plastic Small Outline Large Package 20-Pin (5.3mm-wide) Plastic Shrink Small Outline Package 20-Pin (4.4mm-wide) Plastic Thin Shrink Small Outline Package 20–Pin (300mil–wide) Plastic Dual In–Line Package. 35ns tPD 20–Pin (350mil square) Plastic Leaded Chip Carrier Package 20–Pin (300mil square) Plastic Small Outline Large Package Package 20–Pin (5.3mm–wide) Plastic Shrink Small Outline Package 20–Pin (4.4mm–wide) Plastic Thin shrink Small Outline Package 20-Pin (300mil-wide) Plastic Dual In-Line Package 25ns tPD 20-Pin (350mil square) Plastic Leaded Chip Carrier Package 20-Pin (300mil-wide) Plastic Small Outline Large Package 20-Pin (5.3mm-wide) Plastic Shrink Small Outline Package 20-Pin (4.4mm-wide) Plastic Thin Shrink Small Outline Package 20–Pin (300mil–wide) Plastic Dual In–Line Package, 40ns tPD 20–Pin (350mil square) Plastic Leaded chip Carrier Package 20–Pin (300mil square) Plastic Small Outline Large Package 20–Pin (5.3mm–wide) Plastic Shrink Small Outline Package 20–Pin (4.4mm–wide) Plastic Thin Shrink Small Outline Package Industrial Temperature Range ± 10% Power Supplies Commercial Temperature Range ± 5% Power Supplies TEMPERATURE RANGE ORDER CODE PLC18V8Z25N PLC18V8Z25A PLC18V8Z25D PLC18V8Z25DB PLC18V8Z25DH PLC18V8Z35N PLC18V8Z35A PLC18V8Z35D PLC18V8Z35DB PLC18V8Z35DH PLC18V8ZIAN PLC18V8ZIAA PLC18V8ZIAD PLC18V8ZIADB PLC18V8ZIADH PLC18V8ZIN PLC18V8ZIA PLC18V8ZZID PLC18V8ZIDB PLC18V8ZIDH DRAWING NUMBER SOT146-1 SOT380-1 SOT163-1 SOT339-1 SOT360-1 SOT146–1 SOT380–1 SOT163–1 SOT339–1 SOT260–1 SOT146-1 SOT380-1 SOT163-1 SOT339-1 SOT360-1 SOT146–1 SOT380–1 SOT163–1 SOT339–1 SOT360–1 1997 Aug 08 3 www.DataSheet4U.com Philips Semiconductors Product specification Zero standby power CMOS versatile PAL devices PLC18V8Z PAL DEVICE TO PLC18V8Z OUTPUT PIN CONFIGURATION CROSS REFERENCE PIN NO. 1 19 18 17 16 15 14 13 12 11 PLC 18V8Z I0/CLK F7 F6 F5 F4 F3 F2 F1 F0 I9/OE 16L8 16H8 16P8 16P8 I B B B B B B B B I 16R4 16RP4 CLK B B D D D D B B OE 16R6 16RP6 CLK B D D D D D D B OE 16R8 16RP8 CLK D D D D D D D D OE 16L2 16H2 16P2 I I I I O O I I I I 14L4 14H4 14P4 I I I O O O O I I I 12L6 12H6 12P6 I I O O O O O O I I 10L8 10H8 10P8 I O O O O O O O O I The Philips Semiconductors’ state-of-the-art Floating-Gate CMOS EPROM process yields bipolar equivalent performance at less than one-quarter the power consumption. The erasable nature of the EPROM process enables Philips Semiconductors to functionally test the devices prior to shipment to the customer. Additionally, this allows Philips Semiconductors to extensively stress test, as well as ensure the threshold voltage of each individual EPROM cell. 100% programming yield is subsequently guaranteed. FUNCTIONAL DIAGRAM I0/ CLK 9 I1 PROGRAMMABLE AND ARRAY 36 ROWS X 72 COLUMNS OMC CLK 9 OMC F6 F7 I0 CONFIG. CELL I2 9 OMC F1 I7 9 I8 SP AR OE OMC F0 CONFIG. CELL I9 I9/OE SP00013 1997 Aug 08 4 www.DataSheet4U.com Philips Semiconductors Product specification Zero standby power CMOS versatile PAL devices PLC18V8Z LOGIC DIAGRAM 0 I0/CLK 1 DIR SP 4 8 12 16 20 24 28 32 35 CLK I1 2 DIR AC1 AC2 AR CLK SP OE 19 F7 I2 3 DIR AC1 AC2 AR CLK SP OE 18 F6 I3 4 DIR AC1 AC2 AR CLK OE SP 17 F5 I4 5 DIR AC1 AC2 AR CLK OE SP 16 F4 I5 6 DIR AC1 AC2 AR CLK OE SP 15 F3 I6 7 DIR AC1 AC2 AR CLK OE SP 14 F2 I7 8 DIR AC1 AC2 AR CLK OE SP 13 F1 I8 9 SP AR AC1 AC2 AR CLK OE 12 F0 11 I9/OE CONFIG. CELL I1 I1 F7 F7 I2 I2 F6 F6 I3 I3 F5 F5 I4 I4 F4 F4 I5 I5 F3 F3 I6 I6 F2 F2 I7 I7 F1 F1 I8 I8 F0 F0 I0 I0 I9 I9 NOTES: In the unprogrammed or virgin state: All cells are in a conductive state. All AND gate locations are pulled to a logic “0” (Low). Output polarity is inverting. Pins 1 and 11 are configured as Inputs 0 and 9, respectively, via the configuration cell. The clock and OE functions are disabled. All output macro cells (OMC) are configured as bidirectional I/O, with the outputs disabled via the direction term. Denotes a programmable cell location. SP00012 1997 Aug 08 5 www.DataSheet4U.com Philips Semiconductors Product specification Zero standby power CMOS versatile PAL devices PLC18V8Z OUTPUT MACRO CELL (OMC) 1 FROM AND ARRAY TO ALL OMCs DIRECTION CONTROL TERM 11 VCC 01 OE 00 MUX SP AR 10 FROM AND ARRAY { AC1n AC2n S D X(n) OUTPUT POLARITY CONTROL Q CLK 01 10 OUT 11 MUX 00 F 00 F 10 MUX 11 01 TO ALL OMCs 11 NOTE: Denotes a programmable cell location. OE SP00014 THE OUTPUT MACRO CELL (OMC) The PLC18V8Z series devices have 8 individually programmable Output Macro Cells. The 72 AND inputs (or product terms) from the programmable AND array are connected to the 8 OMCs in groups of 9. Eight of the AND terms are dedicated to logic functions; the ninth is for asynchronous direction control, which enables/disables the respective bidirectional I/O pin. Two product terms are dedicated for the Synchronous Preset and Asynchronous Reset functions. Each OMC can be independently programmed via 16 architecture control bits, AC1n and AC2n (one pair per macro cell). Similarly, each OMC has a programmable output polarity control bit (Xn). By configuring the pair of architecture control bits according to the configuration cell table, 4 different configurations may be implemented. Note that the configuration cell is automatically programmed based on the OMC configuration. DESIGN SECURITY The PLC18V8Z series devices have a programmable security fuse that controls the access to the data programmed in the device. By using this programmable feature, proprietary designs implemented in the device cannot be copied or retrieved. 1997 Aug 08 6 www.DataSheet4U.com Philips Semiconductors Product specification Zero standby power CMOS versatile PAL devices PLC18V8Z CONFIGURATION CELL A single configuration cell controls the functions of Pins 1 and 11. Refer to Functional Diagram. When the configuration cell is programmed, Pin 1 is a dedicated clock and Pin 11 is dedicated for output enable. When the configuration cell is unprogrammed, Pins 1 and 11 are both dedicated inputs. Note that the output enable for all registered OMCs is common—from Pin 11 only. Output enable control of the bidirectional I/O OMCs is provided from the AND array via the direct