3:1 Active HDMI 1.3 Compatible Switch

www.DataSheet4U.com ADVANCE INFORMATION - COMPANY CONFIDENTIAL PI3HDMI341AR 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity Features • Supply voltage, VCC = 3.3V ±5% • Each Port is compatible w/ DVI, HDMI 1.1, HDMI 1.2 or HDMI 1.3 signals • Supports both AC-coupled and DC-coupled inputs • High Performance, up to 1.65 Gbps per channel • Switching support for 3 side band signals (SCL, SDA and HPD) • 5V Tolerance on all side band signals • SCL, SDA, and HPD pins are the only pins that can support HOT INSERTION • Integrated 50-ohm (±10%) termination resistors at each high speed signal input • Configurable output swing control (500mV, 750mV, 1000mV) • Configurable Pre-Emphasis levels (0dB, 1.5dB, 3.5dB, & 6.0dB) • Configurable De-Emphasis (0dB, -3.5dB, -6.0dB, -9.5dB) • Optimized Equalization Single default setting will support all cable lengths • ESD protection = 8kV (typical) on high-speed data channels only • Propagation delay ≤ 2ns • High Impedance Outputs when disabled • Packaging (Pb-free & Green): 80-contact LQFP (FF80) Description Pericom Semiconductor’s PI3HDMI341AR 3:1 active switch circuit is targeted for high-resolution video networks that are based on DVI/HDMI standards and TMDS signal processing. The PI3HDMI341AR is an active 3 TMDS to 1 TMDS receiver switch with Hi-Z outputs. The device receives differential signals from selected video components and drives the video display unit. It provides three controllable output swings that can be controlled through a single bit. The allowable output swings are 500mV, 750mV and 1000mV. This solution also provides a unique advanced pre-emphasis technique to increase rise and fall times which are reduced during transmission across long distances. Each complete HDMI/DVI channel also has slower speed, side band signals, that are required to be switched. Pericom’s solution provides a complete solution by integrating the side band switch together with the high speed switch in a single solution. Using Equalization at the input of each of the high speed channels, Pericom can successfully eliminate deterministic jitter caused by long cables from the source to the sink. The elimination of the deterministic jitter allows the user to use much longer cables (up to 25 meters). The maximum DVI/HDMI Bandwidth of 1.65 Gbps provides 8bit deep color support, which is offered by HDMI revision 1.3. Due to its active uni-directional feature, this switch is designed for usage only for the video receiver’s side. For consumer video networks, the device sits at the receiver’s side to switch between multiple video components, such as PC, DVD, STB, D-VHS, etc. The PI3HDMI341AR is the industry’s first active DVI/HDMI switch compatible with HDMI 1.1, 1.2, and 1.3 which ensures transmitting high-bandwidth video streams from video components to the display unit. The PI3HDMI341AR also provides enhanced robust ESD/EOS protection of 8kV, which is required by many consumer video networks today. The Optimized Equalization provides the user a single optimal setting that can provide HDMI compliance for all cable lengths: 2meter, 10meter, 15meter, and 20 meter. Pericom also offers the ability to fine tune the equalization settings in situations where cable length is known. For example, if 25meter length cable isrequired, Pericom's solution can be adjusted to 16dB EQ to accept 25meter cable length. 06-0340 1 P-1.1 12/20/06 ADVANCE INFORMATION - COMPANY CONFIDENTIAL PI3HDMI341AR 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity Pin Configuration EQ_S1 GND A34 B34 VCC A33 B33 GND A32 B32 VCC A31 B31 GND SCL3 SDA3 HPD3 VCC OE EQ_S0 VCC HPD2 SDA2 SCL2 GND GND B21 A21 VCC B22 A22 GND B23 A23 VCC B24 A24 GND VCC HPD1 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 HPD_SINK SDA_SINK SCL_SINK GND GND Z1 Y1 VCC Z2 Y2 GND Z3 Y3 VCC Z4 Y4 GND S3 S2 S1 OC_S2 OC_S0 OC_S1 VCC GND A14 B14 VCC A13 B13 GND A12 B12 VCC A11 B11 GND SCL1 SDA1 OC_S3 06-0340 2 P-1.1 12/20/06 ADVANCE INFORMATION - COMPANY CONFIDENTIAL PI3HDMI341AR 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity Pin Description Pin # 6,9,12,15 68, 71, 74, 77 49, 52, 55, 58 5, 8, 11, 14 67, 70, 73, 76 48, 51, 54, 57 4, 10, 16 24, 30, 36, 37, 47, 53, 59, 65, 66, 72, 78 80 62 44 40 Pin Name A11, A12, A13, A14 A21, A22, A23, A24 A31, A32, A33, A34 B11, B12, B13, B14 B21, B22, B23, B24 B31, B32, B33, B34 GND HPD1 HPD2 HPD3 HPD_Sink O O O I I/O I I I I I I Description Port 1 TMDS Positive inputs Port 2 TMDS Positive inputs Port 3 TMDS Positive inputs Port 1 TMDS Negative inputs Port 2 TMDS Negative inputs Port 3 TMDS Negative inputs Ground Port 1 HPD output Port 2 HPD output Port 3 HPD output Sink side hot plug detector input. High: 5-V power signal asserted from source to sink and EDID is ready. Low: No 5-V power signal asserted from source to sink, or EDID is not ready. Output Enable, Active LOW Port 1 DDC Clock Port 2 DDC Clock Port 3 DDC Clock Sink Side DDC Data Port 1 DDC Data Port 2 DDC Data Port 3 DDC Data Sink Side DDC Data Source Input Selector 3.3V Power Supply O O I I TMDS positive outputs TMDS negative outputs Equalizer controls(1) Output buffer controls Note: OC_S3 has an internal pull-up resistor. OC_S2 has an internal pull-down resistor. 42 3 64 46 38 2 63 45 39 21,22,23 7, 13, 17 27, 33, 43, 50, 56 61, 69, 75, 79 34, 31, 28, 25 35, 32, 29, 26 41, 60 19, 18, 20, 1 OE SCL1 SCL2 SCL3 SCL_Sink SDA1 SDA2 SDA3 SDA_Sink S1, S2, S3 VCC Y1, Y2, Y3, Y4 Z1, Z2, Z3, Z4 EQ_S0, EQ_S1 OC_S0, OC_S1, OC_S2, OC_S3 I I I I O I/O I/O I/O I/O I Note: 1. EQ_S0 has an internal pull-down and EQ_S1 has an internal pull-up 06-0340 3 P-1.1 12/20/06 ADVANCE INFORMATION - COMPANY CONFIDENTIAL PI3HDMI341AR 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity Switch Block Diagram B11 R e c e iv e r with E Q B12 B13 B14 A11 RINT A12 RINT A13 RINT A14 RINT V CC V CC R e c e iv e r with E Q V CC V CC R e c e iv e r with E Q R e c e iv e r with E Q E2_S0 E2_S1 V CC RINT A24 R e c e iv e r with E Q B24 V CC RINT A23 R e c e iv e r with E Q B23 V CC RINT A22 R e c e iv e r with E Q B22 V CC RINT ... A21 R e c e iv e r with E Q B21 V CC RINT A34 R e c e iv e r with E Q B34 V CC RINT A33 R e c e iv e r with E Q B33 V CC RINT A32 R e c e iv e r with E Q B32 V CC RINT A31 B31 HPD1 HPD2 HPD3 R e c e iv e r with E Q ... SCL1 SDA1 SCL2 SDA2 SCL3 SDA3 06-0340 ... OC_S1 OC_S2 OC_S3 OC_S0 3-to-1 MUX TDMS Drive Y4 Z4 TDMS Drive Y3 Z3 TDMS Drive Y2 Z2 Y1 TDMS Drive Z1 OE S1 S2 S3 Control Logic HPD_SINK SCL_SINK SDA_SINK 4 P-1.1 12/20/06 ADVANCE INFORMATION - COMPANY CONFIDENTIAL PI3HDMI341AR 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity Truth Table Control Pins S1 H L L L S2 x H L L S3 x x H L Y/Z A1/B1 A2/B2 A3/B3 None (Hi-Z) I/O Selected SCL_Sink SDA_Sink SCL1 SDA1 SCL2 SDA2 SCL3 SDA3 None (Hi-Z) HPD1 HPD_Sink L L L Hot Plug Detect Status HPD2 L HPD_Sink L L HPD3 L L HPD_Sink L OC Setting Value Logic Table Input Control Pins OC_S3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 OC_S2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 OC_S1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 OC_S0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Vswing (mV) 500 750 1000 500 500 500 500 500 500 340 270 160 1000 830 500 330 Setting Value Vos (V) 3.06 2.95 2.84 3.02 3.06 3.05 2.97 2.9 3.08 3.08 3.08 3.08 2.85 2.85 2.85 2.85 Pre-emphasis/De-emphasis (dB) none none none none 0 1.5 3.5 6 0 -3.5 -6 -9.5 0 -3.5 -6 -9.5 EQ Setting Value Logic Table EQ_S1 0 0 1 1 EQ_S0 0 1 0 1 Setting Value 3dB on all high speed inputs 8dB on all high speed inputs Optimized Equalization enabled on all high speed inputs (default value if both EQ_S0 and EQ_S1 are left floating) 16dB on all high speed inputs 06-0340 5 P-1.1 12/20/06 ADVANCE INFORMATION - COMPANY CONFIDENTIAL PI3HDMI341AR 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................................... –65°C to +150°C Supply Voltage to Ground Potential................................–0.5V to +4.0V DC Input Voltage ...............................................................–0.5V to VCC DC Output Current....................................................................... 120mA Power Dissipation ........................................................................... 1.0W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended Operating Conditions Symbol VCC TA VID VIC VCC RT Parameter Supply Voltage Operating free-air temperature Receiver peak-to-peak differential input voltage Input common mode voltage TMDS output termination voltage Termination resistance Signaling rate Control Pins (OC_Sx, EQ_Sx, S, OE) VIH VIL VI(DDC) VIH VIL LVTTL High-level input voltage LVTTL Low-level input voltage Input voltage LVTTL High-level input voltage LVTTL Low-level input voltage 2 GND GND 2 GND VCC 0.8 5.5 5.3 0.8 V Min. 3135 0 150 2 3.135 45 0 3.3 50 Typ. 3.3 Max. 3465 70 1560 VCC + 0.01 3.465 55 1.65 Units V °C mVp-p V V ohm Gbps TMDS Differential Pins (A/B) DDC Pins (SCL, SCL_SINK, SDA, SDA_SINK) V Status Pins (HPD_SINK) V 06-0340 6 P-1.1 12/20/06 ADV