Microcontroller

www.DataSheet4U.com Freescale Semiconductor Data Sheet MCF5213EC Rev. 0, 05/2005 MCF5213 Microcontroller Family Hardware Specification The MCF5213 is a member of the ColdFire® family of reduced instruction set computing (RISC) microprocessors. This hardware specification provides an overview of the 32-bit MCF5213 microcontroller, focusing on its highly integrated and diverse feature set. Freescale reserves the right to change or discontinue this product without notice. Specifications and information herein are subject to change without notice. This 32-bit device is based on the Version 2 ColdFire core operating at a frequency up to 80 MHz, offering high performance and low power consumption. On-chip memories connected tightly to the processor core include 256 Kbytes of Flash and 32 Kbytes of static random access memory (SRAM). On-chip modules include the following: • V2 ColdFire core delivering 76 MIPS (Dhrystone 2.1) at 80 MHz running from internal Flash with Multiply Accumulate (MAC) Unit and hardware divider • FlexCAN controller area network (CAN) module • Three universal asynchronous/synchronous receiver/transmitters (UARTs) Table of Contents 1 MCF5213 Family Configurations .........................2 1.1 Block Diagram ...................................................3 1.2 Features.............................................................4 1.3 Part Numbers and Packaging..........................14 1.4 Package Pinouts..............................................15 1.5 Reset Signals ..................................................20 1.6 PLL and Clock Signals ....................................20 1.7 Mode Selection................................................21 1.8 External Interrupt Signals ................................21 1.9 Queued Serial Peripheral Interface (QSPI) .....22 1.10 I2C I/O Signals.................................................22 1.11 UART Module Signals .....................................22 1.12 DMA Timer Signals..........................................23 1.15 Pulse Width Modulator Signals........................24 1.16 Debug Support Signals....................................24 1.17 EzPort Signal Descriptions ..............................26 1.18 Power and Ground Pins...................................26 2 3 Preliminary Electrical Characteristics................26 Mechanical Outline Drawings ............................42 This document contains information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2005. All rights reserved. www.DataSheet4U.com MCF5213 Family Configurations • • • • • • • • • • • • Inter-integrated circuit (I2C™) bus controller Queued serial peripheral interface (QSPI) module Eight-channel 12-bit fast analog-to-digital converter (ADC) Four-channel direct memory access (DMA) controller Four 32-bit input capture/output compare timers with DMA support (DTIM) Four-channel general-purpose timer (GPT) capable of input capture/output compare, pulse width modulation (PWM), and pulse accumulation Eight-channel/Four-channel, 8-bit/16-bit pulse width modulation timer Two 16-bit periodic interrupt timers (PITs) Programmable software watchdog timer Interrupt controller capable of handling 63 selectable-priority interrupt sources Clock module with 8 MHz on-chip relaxation oscillator and integrated phase locked loop (PLL) Test access/debug port (JTAG, BDM) 1 MCF5213 Family Configurations Table 1. MCF5213 Family Configurations Module ColdFire Version 2 Core with MAC (Multiply-Accumulate Unit) System Clock Performance (Dhrystone 2.1 MIPS) Flash / Static RAM (SRAM) Interrupt Controller (INTC) Fast Analog-to-Digital Converter (ADC) FlexCAN 2.0B Module Four-channel Direct-Memory Access (DMA) Software Watchdog Timer (WDT) Programmable Interrupt Timer Four-Channel General Purpose Timer 32-bit DMA Timers QSPI UART(s) I2C Eight/Four-channel 8/16-bit PWM Timer General Purpose I/O Module (GPIO) 5211 x 66 MHz 63 128/16 Kbytes x x x x 2 x 4 x 3 x x x x x x x 2 x 4 x 3 x x x 5212 x 66, 80 MHz up to 76 256/32 Kbytes x x x x x 2 x 4 x 3 x x x 5213 x MCF5213 Microcontroller Family Hardware Specification, Rev. 0 2 Freescale Semiconductor www.DataSheet4U.com MCF5213 Family Configurations Table 1. MCF5213 Family Configurations (continued) Module Chip Configuration and Reset Controller Module Background Debug Mode (BDM) JTAG - IEEE 1149.1 Test Access Port Package NOTES: 1 1 5211 x x x 5212 x x x 5213 x x x 64-pin LQFP 64-pin LQFP 81-ball MAPBGA 81-ball MAPBGA 81-ball MAPBGA 100-Lead LQFP The full debug/trace interface is available only on the 100-pin packages. A reduced debug interface is bonded on smaller packages. 1.1 Block Diagram The MCF5213 comes in a 100-pin low-profile quad flat pack (LQFP) and operates in single-chip mode only. Figure 1 shows a top-level block diagram of the MCF5213. Other members of this family can have different package options, which are described later in this document. MCF5213 Microcontroller Family Hardware Specification, Rev. 0 Freescale Semiconductor 3 www.DataSheet4U.com MCF5213 Family Configurations EzPort EzPCS GPTn QSPI_DIN, QSPI_DOUT QSPI_CLK, QSPI_CSn SDA SCL UTXDn URXDn URTSn UCTSn DTINn/DTOUTn CANRX CANTX PWMn IRQn Arbiter Interrupt Controller PADI – Pin Muxing PMM 4 CH DMA UART 0 UART 1 UART 2 I2C QSPI To/From PADI DTIM 0 DTIM 1 DTIM 2 DTIM 3 JTAG_EN MUX V2 ColdFire CPU JTAG TAP IFP OEP MAC AN[7:0] ADC 32 Kbytes SRAM (4Kx16)x4 VSTBY 256 Kbytes Flash (32Kx16)x4 PORTS (GPIO) CIM RSTI RSTO VRH VRL FlexCAN Edge Port EXTAL PLL OCO CLKGEN XTAL CLKOUT PIT0 PIT1 GPT PWM CLKMOD0 CLKMOD1 To/From Interrupt Controller Figure 1. MCF5213 Block Diagram 1.2 Features This document contains information on a new product under development. Freescale reserves the right to change or discontinue this product without notice. Specifications and information herein are subject to change without notice. MCF5213 Microcontroller Family Hardware Specification, Rev. 0 4 Freescale Semiconductor www.DataSheet4U.com MCF5213 Family Configurations 1.2.1 • Feature Overview Version 2 ColdFire variable-length RISC processor core — Static operation — 32-bit address and data paths on-chip — Up to 80 MHz processor core frequency — Sixteen general-purpose, 32-bit data and address registers — Implements ColdFire ISA_A with extensions to support the user stack pointer register, and four new instructions for improved bit processing — Multiply-Accumulate (MAC) unit with 32-bit accumulator to support 16 × 16 → 32 or 32 × 32 → 32 operations — Illegal instruction decode that allows for 68K emulation support System debug support — Real time trace for determining dynamic execution path — Background debug mode (BDM) for in-circuit debugging — Real time debug support, with six hardware breakpoints (4 PC, 1 address and 1 data) that can be configured into a 1- or 2-level trigger On-chip memories — 32-Kbyte dual-ported SRAM on CPU internal bus, supporting core and DMA access with standby power supply support — 256 Kbytes of interleaved Flash memory supporting 2-1-1-1 accesses Power management — Fully static operation with processor sleep and whole chip stop modes — Very rapid response to interrupts from the low-power sleep mode (wake-up feature) — Clock enable/disable for each peripheral when not used FlexCAN 2.0B Module — Based on and includes all existing features of the Freescale TouCAN module — Full implementation of the CAN protocol specification version 2.0B – Standard Data and Remote Frames (up to 109 bits long) – Extended Data and Remote Frames (up to 127 bits long) – 0-8 bytes data length – Programmable bit rate up to 1 Mbit/sec — Flexible Message Buffers (MBs), totalling up to 16 message buffers of 0–8 byte data length each, configurable as Rx or Tx, all supporting standard and extended messages — Unused MB space can be used as general purpose RAM space — Listen only mode capability — Content-related addressing MCF5213 Microcontroller Family Hardware Specification, Rev. 0 • • • • Freescale Semiconductor 5 www.DataSheet4U.com MCF5213 Family Configurations — No read/write semaphores — Three programmable mask registers: global for MBs 0-13, special for MB14, and special for MB15 — Programmable transmit-first scheme: lowest ID or lowest buffer number — “Time stamp” based on 16-bit free-running timer — Global network time, synchronized by a specific message — Maskable interrupts Three Universal Asynchronous/synchronous Receiver Transmitters (UARTs) — 16-bit divider for clock generation — Interrupt control logic with maskable interrupts — DMA support — Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity — Up to 2 stop bits in 1/16 increments — Error-detection capabilities — Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines for two UARTs — Transmit and receive FIFO buffers I2C Module — Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads — Fully compatible with industry-standard I2C bus — Master and slave modes support multiple masters — Automatic interrupt generation with programmable level Queued Serial Peripheral Interface (QSPI) — Full-duplex, three-wire synchronous transfers — Up to four chip selects available — Master mode operation only — Programmable bit rates up to half the CPU clock frequency — Up to 16 pre-programmed transfers Fast Analog-to-Digital Converter (ADC) — Eight analog input channels — 12-bit resolution ± 2.5 counts accuracy — Minimum 2.25 µs conversion time — Simultaneous sampling of two channels for motor control applications — Single-scan or continuous operation — Optional interrupts on conversion complete, zero crossing (sign change), or under/over low/high limit — Unused analog channels c