Search -----> STP120NF

www.DataSheet4U.com STP120NF04 N-CHANNEL 40V - 0.0047Ω - 120A TO-220 STripFET™II MOSFET Table 1: General Features TYPE STP120NF04 s s s Figure 1: Package ID (1) Pw VDSS 40 V RDS(on) < 0.0050Ω 120 A 300 W TYPICAL RDS(on) = 0.0047 Ω STANDARD THRESHOLD DRIVE 100% AVALANCHE TESTED 3 DESCRIPTION This MOSFET is the latest development of STMicroelectronics unique “Single Feature Size™” strip-based process. The resulting transistor shows extremely high packing density for low onresistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. APPLICATIONS s HIGH CURRENT, HIGH SWITCHING SPEED 1 2 TO-220 Figure 2: Internal Schematic Diagram Table 2: Order Codes Part Number STP120NF04 Marking P120NF04 Package TO-220 Packaging TUBE Rev. 1 February 2005 1/11 www.DataSheet4U.com STP120NF04 Table 3: Absolute Maximum ratings Symbol VDS VDGR VGS ID (#) ID IDM ( ) PTOT dv/dt (1) EAS (2) Tj Tstg Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 kΩ) Gate- source Voltage Drain Current (continuos) at TC = 25°C Drain Current (continuos) at TC = 100°C Drain Current (pulsed) Total Dissipation at TC = 25°C Derating Factor Peak Diode Recovery voltage slope Single Pulse Avalanche Energy Operating Junction Temperature Storage Temperature Value 40 40 ± 20 120 120 480 300 2 6 1.2 -55 to 175 Unit V V V A A A W W/°C V/ns J °C ( ) Pulse width limited by safe operating area (1) ISD ≤120A, di/dt ≤300A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX. (2) Starting Tj = 25°C, Id = 60A, VDD=30 V (#) Current Limited by Package Table 4: Thermal Data Rthj-case Rthj-pcb Rthj-amb Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-pcb Max Thermal Resistance Junction-ambient (Free air) Max Maximum Lead Temperature For Soldering Purpose 0.5 See Curve on page 6 62.5 300 °C/W °C/W °C/W °C ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) Table 5: On /Off Symbol V(BR)DSS IDSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Gate Threshold Voltage Static Drain-source On Resistance Test Conditions ID = 250 µA, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 °C VGS = ± 20V VDS = VGS, ID = 250µA VGS = 10V, ID = 50 A 2.8 0.0047 Min. 40 Typ. Max. Unit V 1 10 ±100 4.5 0.0050 µA µA nA V Ω IGSS VGS(th) RDS(on) Table 6: Dynamic Symbol gfs (1) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS > =15 V , ID =50 A VDS = 25 V, f = 1 MHz, VGS = 0 Min. Typ. 150 5100 1300 160 Max. Unit S pF pF pF 2/11 www.DataSheet4U.com STP120NF04 ELECTRICAL CHARACTERISTICS (CONTINUED) Table 7: Switching On Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDD = 20 V, ID = 60 A RG = 4.7Ω VGS = 10 V (see, Figure 20) VDD = 32V, ID = 120 A, VGS = 10V (see, Figure 22) Min. Typ. 35 220 110 35 35 150 Max. Unit ns ns nC nC nC Table 8: Switching Symbol td(off) tf Parameter Turn-off Delay Time Fall Time Test Conditions VDD = 20 V, ID = 60 A RG = 4.7Ω VGS = 10 V ( see Figure 20 ) Min. Typ. 80 50 Max. Unit ns ns Table 9: Source Drain Diode Symbol ISD ISDM (2) VSD (1) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 120 A, VGS = 0 ISD = 120 A, di/dt = 100A/µs VDD = 20V, Tj = 150°C (see test circuit, Figure 21) 75 185 5 Test Conditions Min. Typ. Max. 120 480 1.3 Unit A A V ns nC A (1) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. (2) Pulse width limited by safe operating area. 3/11 www.DataSheet4U.com STP120NF04 Figure 3: Safe Operating Area Figure 6: Thermal Impedance Figure 4: Output Characteristics Figure 7: Transfer Characteristics Figure 5: Transconductance Figure 8: Static Drain-source On Resistance 4/11 www.DataSheet4U.com STP120NF04 Figure 12: Capacitance Variation Figure 9: Gate Charge vs Gate-source Voltage Figure 10: Normalized Gate Thereshold Voltage vs Temperature Figure 13: Normalized BVDSS vs Temperature Figure 11: Normalized On Resistance vs Temperature Figure 14: Source-Drain Diode Forward Characteristics 5/11 www.DataSheet4U.com STP120NF04 Figure 15: Power Derating vs Tc Figure 17: Thermal Resistance Rthj-a vs PCB Copper Area Figure 16: Max Id Current vs Tc Figure 18: Max Power Dissipation vsPCB Copper Area 6/11 www.DataSheet4U.com STP120NF04 Figure 19: Allowable lav vs Time in Avalanche The previous curve gives the safe operating area for unclamped inductive loads, single pulse or repetitive, under the following conditions: PD(AVE) = 0.5 * (1.3 * BVDSS * IAV) EAS(AR) = PD(AVE) * tAV Where: IAV is the Allowable Current in Avalanche PD(AVE) is the Average Power Dissipation in Avalanche (Single Pulse) tAV is the Time in Avalanche To derate above 25 °C, at fixed IAV, the following equation must be applied: IAV = 2 * (Tjmax - TCASE) / (1.3 * BVDSS * Zth) Where: Zth = K * Rth is the value coming from Normalized Thermal Response at fixed pulse width equal to TAV. 7/11 www.DataSheet4U.com STP120NF04 Figure 20: Switching Times Test Circuit For Resistive Load Figure 22: Gate Charge Test Circuit Figure 21: Test Circuit For Diode Recovery Times 8/11 www.DataSheet4U.com STP120NF04 TO-220 MECHANICAL DATA DIM. A b b1 c D E e e1 F H1 J1 L L1 L20 L30 mm. MIN. 4.40 0.61 1.15 0.49 15.25 10 2.40 4.95 1.23 6.20 2.40 13 3.50 16.40 28.90 3.75 2.65 3.85 2.95 0.147 0.104 TYP MAX. 4.60 0.88 1.70 0.70 15.75 10.40 2.70 5.15 1.32 6.60 2.72 14 3.93 MIN. 0.173 0.024 0.045 0.019 0.60 0.393 0.094 0.194 0.048 0.244 0.094 0.511 0.137 0.645 1.137 0.151 0.116 inch TYP. MAX. 0.181 0.034 0.066 0.027 0.620 0.409 0.106 0.202 0.052 0.256 0.107 0.551 0.154 øP Q 9/11 www.DataSheet4U.com STP120NF04 Table 10: Revision History Date 15-Feb-2005 Revision 1 First Release. Description of Changes 10/11 www.DataSheet4U.com STP120NF04 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners © 2005 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 11/11