Power MOSFET

www.DataSheet4U.com NTTD1P02R2 Power MOSFET −1.45 Amps, −20 Volts P−Channel Enhancement Mode Dual Micro8 Package Features • • • • • • Ultra Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Miniature Dual Micro8 Surface Mount Package Diode Exhibits High Speed, Soft Recovery Micro8 Mounting Information Provided http://onsemi.com −1.45 AMPERES −20 VOLTS 160 mW @ VGS = −4.5 Dual P−Channel D Applications • Power Management in Portable and Battery−Powered Products, i.e.: Computers, Printers, PCMCIA Cards, Cellular and Cordless Telephones MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Drain−to−Source Voltage Gate−to−Source Voltage − Continuous Thermal Resistance − Junction−to−Ambient (Note 1.) Total Power Dissipation @ TA = 25°C Continuous Drain Current @ TA = 25°C Continuous Drain Current @ TA = 70°C Pulsed Drain Current (Note 3.) Thermal Resistance − Junction−to−Ambient (Note 2.) Total Power Dissipation @ TA = 25°C Continuous Drain Current @ TA = 25°C Continuous Drain Current @ TA = 70°C Pulsed Drain Current (Note 3.) Operating and Storage Temperature Range Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = −20 Vdc, VGS = −4.5 Vdc, Peak IL = −3.5 Apk, L = 5.6 mH, RG = 25 Ω) Maximum Lead Temperature for Soldering Purposes for 10 seconds Symbol VDSS VGS RθJA PD ID ID IDM RθJA PD ID ID IDM TJ, Tstg EAS Value −20 "8.0 250 0.50 −1.45 −1.15 −10 125 1.0 −2.04 −1.64 −16 −55 to +150 35 Unit V V G S °C/W W A A A °C/W W A A A °C mJ Source 1 Gate 1 Source 2 Gate 2 TL 260 °C 1 8 2 YWW 7 3 6 BC 4 5 (Top View) Y = Year WW = Work Week BC = Device Code Drain 1 Drain 1 Drain 2 Drain 2 8 1 Micro8 CASE 846A STYLE 2 MARKING DIAGRAM & PIN ASSIGNMENT 1. Minimum FR−4 or G−10 PCB, Steady State. 2. Mounted onto a 2″ square FR−4 Board (1″ sq. 2 oz Cu 0.06″ thick single sided), Steady State. 3. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%. ORDERING INFORMATION Device NTTD1P02R2 Package Micro8 Shipping† 4000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2003 1 December, 2003 − Rev. 1 Publication Order Number: NTTD1P02R2/D NTTD1P02R2 ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) (Note 4.) Characteristic OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (VGS = 0 Vdc, ID = −250 µAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = −20 Vdc, TJ = 25°C) (VGS = 0 Vdc, VDS = −20 Vdc, TJ = 125°C) Gate−Body Leakage Current (VGS = −8 Vdc, VDS = 0 Vdc) Gate−Body Leakage Current (VGS = +8 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = −250 µAdc) Temperature Coefficient (Negative) Static Drain−to−Source On−State Resistance (VGS = −4.5 Vdc, ID = −1.45 Adc) (VGS = −2.7 Vdc, ID = −0.7 Adc) (VGS = −2.5 Vdc, ID = −0.7 Adc) Forward Transconductance (VDS = −10 Vdc, ID = −0.7 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 5. & 6.) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Total Gate Charge Gate−Source Charge Gate−Drain Charge BODY−DRAIN DIODE RATINGS (Note 5.) Diode Forward On−Voltage (IS = −1.45 Adc, VGS = 0 Vdc) (IS = −1.45 Adc, VGS = 0 Vdc, TJ = 125°C) (IS = −1.45 Adc, VGS = 0 Vdc, 1 45 Ad Vd dIS/dt = 100 A/µs) Reverse Recovery Stored Charge 4. Handling precautions to protect against electrostatic discharge is mandatory. 5. Indicates Pulse Test: Pulse Width = 300 µs max, Duty Cycle = 2%. 6. Switching characteristics are independent of operating junction temperature. VSD − − − − − − −0.91 −0.72 25 13 12 0.015 −1.1 − − − − − µC Vdc (VDS = −16 Vdc, VGS = −4.5 Vdc, ID = −1.45 Adc) 1 45 Ad ) (VDD = −16 Vdc, ID = −0.7 Adc, 16 0.7 VGS = −4.5 Vdc, RG = 6.0 Ω) (VDD = −16 Vdc, ID = −1.45 Adc, 16 1.45 VGS = −4.5 Vdc, RG = 6.0 Ω) td(on) tr td(off) tf td(on) tr td(off) tf Qtot Qgs Qgd − − − − − − − − − − − 10 25 30 25 10 20 30 20 5.0 1.5 2.0 − − − − − − − − 10 − − nC ns ns (VDS = −16 Vdc, VGS = 0 Vdc, 16 Vd Vd f = 1.0 MHz) Ciss Coss Crss − − − 265 100 60 − − − pF VGS(th) −0.7 − RDS(on) − − − gFS − 0.130 0.175 0.190 2.5 0.160 0.250 − − Mhos −0.95 2.3 −1.4 − Ω Vdc V(BR)DSS −20 − IDSS − − IGSS − IGSS − − 100 − −100 nAdc − − −1.0 −10 nAdc − −12 − − Vdc mV/°C µAdc Symbol Min Typ Max Unit Reverse Recovery Time trr ta tb QRR ns http://onsemi.com 2 NTTD1P02R2 3 −2.7 V −2.9 V −3.1 V −3.3 V −3.7 V −4.5 V 2 −8 V −1.9 V 1 −1.7 V VGS = −1.5 V 0 0 0.25 0.5 0.75 1 1.25 1.5 1.75 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 3 −2.5 V TJ = 25°C −2.1 V −ID, DRAIN CURRENT (AMPS) −2.3 V VDS ≥ −10 V −ID, DRAIN CURRENT (AMPS) 2 TJ = −55°C 1 TJ = 100°C TJ = 25°C 0 0 0.5 1 1.5 2 2.5 3 3.5 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) Figure 2. Transfer Characteristics 0.4 0.3 TJ = 25°C VGS = −2.5 V 0.2 VGS = −2.7 V VGS = −4.5 V 0.3 ID = −1.45 A TJ = 25°C 0.2 0.1 0.1 0 0 2 4 6 8 10 12 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 0 0 0.5 1 1.5 2 2.5 3 3.5 −ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance versus Gate−to−Source Voltage Figure 4. On−Resistance versus Drain Current and Gate Voltage 1.6 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) ID = −1.45 A VGS = −4.5 V 100 VGS = 0 V −IDSS, LEAKAGE (nA) TJ = 125°C 1.4 1.2 10 TJ = 100°C 1 0.8 0.6 −50 1 −25 0 25 75 50 100 125 TJ, JUNCTION TEMPERATURE (°C) 150 4 8 12 16 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 20 Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 3 NTTD1P02R2 800 Ciss C, CAPACITANCE (pF) 600 Crss 400 Ciss 200 Coss 0 10 5 0 −VGS −VDS 5 10 15 Crss 20 VDS = 0 V VGS = 0 V TJ = 25°C 5 QT 4 −VGS Q1 2 ID = −1.45 A TJ = 25°C Q2 20 18 16 14 12 10 8 6 1 0 0 1 2 3 4 5 6 Qg, TOTAL GATE CHARGE (nC) −VDS 4 2 0 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 1 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 3 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge Figure 7. Capacitance Variation 100 −IS, SOURCE CURRENT (AMPS) VDD = −16 V ID = −1.45 A VGS = −4.5 V t, TIME (ns) 1.6 VGS = 0 V TJ = 25°C 1.2 10 td (off) tf td (on) tr 0.8 0.4 1 1 10 RG, GATE RESISTANCE (OHMS) 100 0 0.4 0.5 0.6 0.7 0.8 0.9 −VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Variation versus Gate Resistance 100 ID , DRAIN CURRENT (AMPS) Figure 10. Diode Forward Voltage versus Current VGS = 8 V SINGLE PULSE TC = 25°C 100 ms 1 ms IS di/dt 10 trr ta tb TIME tp 0.25 IS IS 1 10 ms 0.1 0.01 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 dc 100 Figure 12. Diode Reverse Recovery Waveform VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 11. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 4 NTTD1P02R2 TYPICAL ELECTRICAL CHARACTERISTICS 1000 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (°C/W) 100 D = 0.5 0.2 0.1 0.05 0.02 0.01 10 P(pk) 1 SINGLE PULSE 0.1 1.0E−05 1.0E−04 1.0E−03 1.0E−02 1.0E−01 t, TIME (s) t2 DUTY CYCLE, D = t1/t2 1.0E+00 t1 RθJC(t) = r(t) RθJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RθJC(t) 1.0E+01 1.0E+02 1.0E+03 Figure 13. Thermal Response http://onsemi.com 5 NTTD1P02R2 PACKAGE DIMENSIONS Micro8 CASE 846A−02 ISSUE F −A− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. 846A−01 OBSOLETE, NEW STANDARD 846A−02. DIM A B C D G H J K L MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 −−− 1.10 0.25 0.40 0.65 BSC 0.05 0.15 0.13 0.23 4.75 5.05 0.40 0.70 INCHES MIN MAX 0.114 0.122 0.114 0.122 −−− 0.043 0.010 0.016 0.026 BSC 0.002 0.006 0.005 0.009 0.187 0.199 0.016 0.028 K −B− PIN 1 ID G D 8 PL 0.08 (0.003) M TB S A S −T− PLANE 0.038 (0.0015) H SEATING C J L STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. SOURCE 1 GATE 1 SOURCE 2 GATE 2 DRAIN 2 DRAIN 2 DRAIN 1 DRAIN 1 SOLDERING FOOTPRINT* 8X 1.04 0.041 0.38 0.015 8X 3.20 0.126 4.24 0.167 5.28 0.208 6X 0.65 0.0256 SCALE 8:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Micro8 is a trademark of International Rectifier. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or speci