Power MOSFET

NTMS3P03R2 Power MOSFET −3.05 Amps, −30 Volts P−Channel SOIC−8 Features http://onsemi.com • • • • • • • • High Efficiency Components in a Single SOIC−8 Package High Density Power MOSFET with Low RDS(on) Miniature SOIC−8 Surface Mount Package − Saves Board Space Diode Exhibits High Speed with Soft Recovery IDSS Specified at Elevated Temperature Avalanche Energy Specified Mounting Information for the SOIC−8 Package is Provided Pb−Free Package is Available −3.05 AMPERES −30 VOLTS 0.085 W @ VGS = −10 V P−Channel D Applications G S • DC−DC Converters • Low Voltage Motor Control • Power Management in Portable and Battery−Powered Products, i.e.: Computers, Printers, PCMCIA Cards, Cellular & Cordless Telephones www.DataSheet4U.com MARKING DIAGRAM & PIN ASSIGNMENT 8 1 SOIC−8 CASE 751 STYLE 13 8 D D DD E3P03 AYWW G G 1 NC S SG E3P03 A Y WW G = Specific Device Code = Assembly Location = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device NTMS3P03R2 NTMS3P03R2G Package SOIC−8 SOIC−8 (Pb−Free) Shipping† 2500/Tape & Reel 2500/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2006 March, 2006 − Rev. 2 1 Publication Order Number: NTMS3P03R2/D NTMS3P03R2 MAXIMUM RATINGS Rating Drain−to−Source Voltage Gate−to−Source Voltage − Continuous Thermal Resistance − Junction−to−Ambient (Note 1) Total Power Dissipation @ TA = 25°C Continuous Drain Current @ 25°C Continuous Drain Current @ 70°C Pulsed Drain Current (Note 4) Thermal Resistance − Junction−to−Ambient (Note 2) Total Power Dissipation @ TA = 25°C Continuous Drain Current @ 25°C Continuous Drain Current @ 70°C Pulsed Drain Current (Note 4) Thermal Resistance − Junction−to−Ambient (Note 3) Total Power Dissipation @ TA = 25°C Continuous Drain Current @ 25°C Continuous Drain Current @ 70°C Pulsed Drain Current (Note 4) Operating and Storage Temperature Range Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = −30 Vdc, VGS = −4.5 Vdc, Peak IL = −7.5 Apk, L = 5 mH, RG = 25 W) Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds Symbol VDSS VGS RqJA PD ID ID IDM RqJA PD ID ID IDM RqJA PD ID ID IDM TJ, Tstg EAS TL Value −30 ±20 171 0.73 −2.34 −1.87 −8.0 100 1.25 −3.05 −2.44 −12 62.5 2.0 −3.86 −3.1 −15 −55 to +150 140 260 Unit V V °C/W W A A A °C/W W A A A °C/W W A A A °C mJ °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Minimum FR−4 or G−10 PCB, t = steady state. 2. Mounted onto a 2″ square FR−4 Board (1″ sq. 2 oz Cu 0.06″ thick single sided), t = steady state. 3. Mounted onto a 2″ square FR−4 Board (1″ sq. 2 oz Cu 0.06″ thick single sided), t ≤ 10 seconds. 4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%. http://onsemi.com 2 NTMS3P03R2 ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) (Note 5) Characteristic OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (VGS = 0 Vdc, ID = −250 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = −30 Vdc, VGS = 0 Vdc, TJ = 25°C) (VDS = −30 Vdc, VGS = 0 Vdc, TJ = 125°C) Gate−Body Leakage Current (VGS = −20 Vdc, VDS = 0 Vdc) Gate−Body Leakage Current (VGS = +20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = −250 mAdc) Temperature Coefficient (Negative) Static Drain−to−Source On−State Resistance (VGS = −10 Vdc, ID = −3.05 Adc) (VGS = −4.5 Vdc, ID = −1.5 Adc) Forward Transconductance (VDS = −15 Vdc, ID = −3.05 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 6 & 7) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Total Gate Charge Gate−Source Charge Gate−Drain Charge BODY−DRAIN DIODE RATINGS (Note 6) Diode Forward On−Voltage Reverse Recovery Time (IS = −3.05 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) Reverse Recovery Stored Charge 5. Handling precautions to protect against electrostatic discharge is mandatory. 6. Indicates Pulse Test: Pulse Width = 300 ms max, Duty Cycle = 2%. 7. Switching characteristics are independent of operating junction temperature. (IS = −3.05 Adc, VGS = 0 V) (IS = −3.05 Adc, VGS = 0 V, TJ = 125°C) VSD trr ta tb QRR − − − − − − −0.96 −0.78 34 18 16 0.03 −1.25 − − − − − mC Vdc ns (VDS = −24 Vdc, VGS = −10 Vdc, ID = −3.05 Adc) (VDD = −24 Vdc, ID = −1.5 Adc, VGS = −4.5 Vdc, RG = 6.0 W) (VDD = −24 Vdc, ID = −3.05 Adc, VGS = −10 Vdc, RG = 6.0 W) td(on) tr td(off) tf td(on) tr td(off) tf Qtot Qgs Qgd − − − − − − − − − − − 12 16 45 45 16 42 32 35 16 2.0 4.5 22 30 80 80 − − − − 25 − − nC ns ns (VDS = −24 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss Coss Crss − − − 520 170 70 750 325 135 pF VGS(th) −1.0 − − − − −1.7 3.6 0.063 0.090 5.0 −2.5 − 0.085 0.115 − Vdc V(BR)DSS −30 − − − − − − −30 − − − − − − −1.0 −10 −100 100 Vdc mV/°C mAdc Symbol Min Typ Max Unit IDSS IGSS IGSS nAdc nAdc RDS(on) W gFS Mhos http://onsemi.com 3 NTMS3P03R2 TYPICAL ELECTRICAL CHARACTERISTICS 6 −ID, DRAIN CURRENT (AMPS) 5 4 TJ = 25°C 3 2 1 0 6 −ID, DRAIN CURRENT (AMPS) VGS = −4.4 V VGS = −4 V VGS = −4.6 V VGS = −4.8 V VGS = −3.6 V VGS = −2.8 V VGS = −3.2 V VGS = −5 V VGS = −2.6 V VGS = −3 V VDS > = −10 V 5 4 TJ = 100°C 3 2 1 0 TJ = 25°C TJ = −55°C VGS = −10 V VGS = −8 V VGS = −6 V 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 1 2 3 4 5 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 3 4 5 6 7 8 ID = −3.05 A TJ = 25°C RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2 Figure 2. Transfer Characteristics ID = −1.5 A TJ = 25°C 3 4 5 6 7 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 3. On−Resistance vs. Gate−to−Source Voltage RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 0.25 TJ = 25°C 0.2 VGS = −4.5 V 1.6 1.4 Figure 4. On−Resistance vs. Gate−to−Source Voltage ID = −3.05 A VGS = −10 V 1.2 1 0.8 0.6 −50 0.15 VGS = −10 V 0.1 0.05 1 2 3 4 5 6 −25 0 25 50 75 100 125 150 −ID, DRAIN CURRENT (AMPS) TJ, JUNCTION TEMPERATURE (°C) Figure 5. On−Resistance vs. Drain Current and Gate Voltage Figure 6. On Resistance Variation with Temperature http://onsemi.com 4 NTMS3P03R2 10000 VGS = 0 V C, CAPACITANCE (pF) TJ = 150°C 1200 1000 800 600 400 200 VDS = 0 V VGS = 0 V IDSS, LEAKAGE (nA) Ciss 1000 TJ = 125°C 100 Crss Ciss Coss TJ = 25°C −VGS Crss 0 5 10 15 20 25 30 10 6 10 14 18 22 26 30 0 10 5 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) −VDS −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Drain−to−Source Leakage Current vs. Voltage 12 10 8 6 4 2 0 Q1 Q2 VDS VGS 15 10 5 0 16 1 QT 30 1000 25 20 100 Figure 8. Capacitance Variation VDS = −24 V ID = −3.05 A VGS = −10 V td(off) tf 10 tr td(on) ID = −3.05 A TJ = 25°C 0 2 4 6 8 10 12 14 Qg, TOTAL GATE CHARGE (nC) t, TIME (ns) 1 10 RG, GATE RESISTANCE (W) 100 Figure 9. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge 1000 VDS = −24 V ID = −1.5 A VGS = −4.5 V 3 IS, SOURCE CURRENT (AMPS) 2.5 2 1.5 1 0.5 Figure 10. Resistive Switching Time Variation vs. Gate Resistance VGS = 0 V TJ = 25°C t, TIME (ns) 100 tr tf td(off) td(on) 10 1 10 RG, GATE RESISTANCE (W) 100 0 0.2 0.4 0.6 0.8 1 1.2 −VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 11. Resistive Switching Time Variation vs. Gate Resistance Figure 12. Diode Forward Voltage vs. Current http://onsemi.com 5 NTMS3P03R2 100 −ID, DRAIN CURRENT (AMPS) 10 VGS = 12 V SINGLE PULSE TA = 25°C 1.0 ms di/dt IS trr ta tb TIME tp 10 100 IS 0.25 IS 10 ms 1.0 dc 0.1 RDS(on) THERMAL LIMIT PACKAGE LIMIT 1.0 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0.01 0.1 Figure 13. Maximum Rated Forward Biased Safe Operating Area Figure 14. Diode Reverse Recovery Waveform 1.0 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESPONSE D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 Single Pulse 1E−02 1E−01 1E+00 t, TIME (s) 1E+01 1E+02 Normalized to RqJA at Steady State (1″ pad) Chip Junction 2.32 W 18.5 W 50.9 W 37.1 W 56.8 W 24.4 W 0.0014 F 0.0073 F 0.022 F 0.105 F 0.484 F 3.68 F Ambient 1E+03 0.01 1E−03 Figure 15. FET Thermal Response http://onsemi.com 6 NTMS3P03R2 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AG −X− A 8 5 B 1 S 4 0.25 (0.010) M Y M −Y− G K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. MILLIMETERS DIM MIN MAX A 4.80 5.00 B 3.80 4.00 C 1.35 1.75 D 0.33 0.51 G 1.27 BSC H 0.10 0.25 J 0.19 0.25 K 0.40 1.27 M 0_ 8_ N 0.25 0.50 S 5.80 6.20 STYLE 13