Power MOSFET

NTHD4401P Power MOSFET −20 V, −3.0 A, Dual P−Channel, ChipFETt Features • Low RDS(on) and Fast Switching Speed in a ChipFET Package • Leadless ChipFET Package 40% Smaller Footprint than TSOP−6 • ChipFET Package with Excellent Thermal Capabilities where Heat • Pb−Free Package is Available Applications http://onsemi.com Transfer is Required V(BR)DSS −20 V RDS(on) TYP 130 mW @ −4.5 V ID MAX −3.0 A 200 mW @ −2.5 V • Charge Control in Battery Chargers • Optimized for Battery and Load Management Applications in Portable Equipment • MP3 Players, Cell Phones, Digital Cameras, PDAs • Buck and Boost DC−DC Converters MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Drain−to−Source Voltage Gate−to−Source Voltage Continuous Drain Current (Note 1) Steady State tv5s Power Dissipation (Note 1) Steady State tv5s Pulsed Drain Current TA = 25°C TA = 85°C TA = 25°C TA = 25°C TA = 85°C TA = 25°C IDM TJ, Tstg IS TL PD Symbol VDSS VGS ID Value −20 "12 −2.1 −1.5 −3.0 1.1 0.6 2.1 −9.0 −55 to 150 −2.5 260 A °C A °C D1 8 D1 7 D2 6 D2 5 W Unit V V A G1 S1 S2 G2 D1 P−Channel MOSFET D2 P−Channel MOSFET www.DataSheet4U.com ChipFET CASE 1206A STYLE 2 PIN CONNECTIONS 1 S1 2 G1 3 S2 4 G2 1 MARKING DIAGRAM 8 C4 M G 7 6 5 tp = 10 ms Operating Junction and Storage Temperature Source Current (Body Diode) Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) 2 3 4 THERMAL RESISTANCE RATINGS Rating Junction−to−Ambient − Steady State (Note 1) Junction−to−Ambient − t v 5 s Symbol RqJA Value 110 60 Unit °C/W C4 = Specific Device Code M = Month Code G = Pb−Free Package ORDERING INFORMATION Device NTHD4401PT1 NTHD4401PT1G Package ChipFET ChipFET (Pb−Free) Shipping † 3000/Tape & Reel 3000/Tape & Reel Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq [1 oz] including traces). †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Publication Order Number: NTHD4401P/D © Semiconductor Components Industries, LLC, 2005 1 November, 2005 − Rev. 4 NTHD4401P ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage Drain−to−Source Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current V(Br)DSS V(Br)DSS/TJ IDSS VGS = 0 V VDS = −16 V Gate−to−Source Leakage Current ON CHARACTERISTICS (Note 2) Gate Threshold Voltage Gate Threshold Temperature Coefficient Drain−to−Source On Resistance VGS(th) VGS(th)/TJ RDS(on) VGS = −4.5 V, ID = −2.1 A VGS = −2.5 V, ID = −1.7 A VGS = −1.8 V, ID = −1.0 A VDS = −10 V, ID = −2.1 A VGS = VDS, ID = −250 mA −0.6 −0.75 2.65 0.130 0.200 0.34 5.0 0.155 0.240 −1.2 V mV/°C W IGSS TJ = 25°C TJ = 85°C VGS = 0 V, ID = −250 mA −20 −23 −8.0 −1.0 −5.0 "100 nA V mV/°C mA Symbol Test Condition Min Typ Max Unit VDS = 0 V, VGS = "12 V Forward Transconductance gFS S CHARGES, CAPACITANCES AND GATE RESISTANCE Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Threshold Gate Charge Gate−to−Source Charge Gate−to−Drain Charge SWITCHING CHARACTERISTICS (Note 3) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge VSD trr ta tb QRR VGS = 0 V, dIS/dt = 90 A/ms, IS = −2.1 A VGS = 0 V IS = −2.5 A −0.85 32 10 22 15 nC ns −1.15 V td(on) tr td(off) tf VGS = −4.5 V, VDD = −16 V, ID = −2.1 A, RG = 2.5 W 7.0 13 33 27 12 25 50 40 ns Ciss Coss Crss QG(TOT) QG(TH) QGS QGD VGS = −4.5 V, VDS = −10 V, ID = −2.1 A VGS = 0 V, f = 1.0 MHz, VDS = −10 V 185 95 30 3.0 0.2 0.5 0.9 nC 300 150 50 6.0 pF 2. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%. 3. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 NTHD4401P TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) 4 −ID, DRAIN CURRENT (AMPS) VGS = −6 V to −3 V VGS = −2.4 V −2.2 V TJ = 25°C −ID, DRAIN CURRENT (AMPS) −2 V 4 VDS ≥ −10 V 3 3 −1.8 V 2 −1.6 V 1 −1.4 V −1.2 V 0 0 1 2 3 4 5 6 7 8 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 2 TC = −55°C 25°C 0 0.5 100°C 3 1 1 1.5 2 2.5 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0.5 ID = −2.1 A TJ = 25°C 0.25 Figure 2. Transfer Characteristics TJ = 25°C 0.225 0.2 0.175 0.15 0.125 0.1 0.5 VGS = −4.5 V VGS = −2.5 V 0.4 0.3 0.2 0.1 0 1 2 3 4 5 6 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 1.5 2.5 3.5 4.5 −ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance vs. Gate−to−Source Voltage 1.6 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) ID = −2.1 A VGS = −4.5 V 1.4 Figure 4. On−Resistance vs. Drain Current and Gate Voltage ID = −1.0 A VGS = −1.8 V 1.2 1.2 1 1 0.8 0.6 −50 −25 0 25 50 75 100 125 150 0.8 −50 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 5. On−Resistance Variation with Temperature Figure 6. On−Resistance Variation with Temperature http://onsemi.com 3 NTHD4401P TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) 10000 VGS = 0 V 500 C, CAPACITANCE (pF) −IDSS, LEAKAGE (A) TJ = 150°C 1000 400 300 200 100 10 2 4 6 8 10 12 14 16 18 20 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0 10 5 0 −VGS −VDS 5 10 15 20 Coss Crss 600 VDS = 0 V Ciss VGS = 0 V TJ = 25°C 100 TJ = 100°C Figure 7. Drain−to−Source Leakage Current vs. Voltage −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 6 −VDS 5 4 −VGS 3 2 1 0 0 0.5 1 1.5 2 2.5 Qg, TOTAL GATE CHARGE (nC) 3 Q1 Q2 6 4 ID = −2.1 A TJ = 25°C 2 0 3.5 QT 12 10 8 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 100 Figure 8. Capacitance Variation tf td(off) t, TIME (ns) tr 10 td(on) VDD = −16 V ID = −2.1 A VGS = −4.5 V 1 1 10 RG, GATE RESISTANCE (OHMS) 100 Figure 9. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge 2.5 −IS, SOURCE CURRENT (AMPS) VGS = 0 V TJ = 25°C 2 Figure 10. Resistive Switching Time Variation vs. Gate Resistance 1.5 1 0.5 0 0.3 0.5 0.7 0.9 −VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 11. Diode Forward Voltage vs. Current http://onsemi.com 4 NTHD4401P 1.0 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE 1.0E−02 1.0E−01 1.0E+00 t, TIME (s) 0.0154 F 0.0854 F 0.3074 F 1.7891 F 107.55 F 0.1 Normalized to θJA at 10s. Chip 0.0175 Ω 0.0710 Ω 0.2706 Ω 0.5776 Ω 0.7086 Ω Ambient 1.0E+03 0.01 1.0E−03 1.0E+01 1.0E+02 Figure 12. Thermal Response SOLDERING FOOTPRINT* 2.032 0.08 0.457 0.018 0.635 0.025 0.635 0.025 1.092 0.043 2.032 0.08 0.178 0.007 0.457 0.018 0.711 0.028 0.66 0.026 SCALE 20:1 mm inches 0.66 0.026 0.254 0.010 SCALE 20:1 mm inches Figure 13. Basic Figure 14. Style 2 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. BASIC PAD PATTERNS The basic pad layout with dimensions is shown in Figure 13. This is sufficient for low power dissipation MOSFET applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. The minimum recommended pad pattern shown in Figure 14 improves the thermal area of the drain connections (pins 5, 6, 7, 8) while remaining within the confines of the basic footprint. The drain copper area is 0.0019 sq. in. (or 1.22 sq. mm). This will assist the power dissipation path away from the device (through the copper leadframe) and into the board and exterior chassis (if applicable) for the single device. The addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further. http://onsemi.com 5 NTHD4401P PACKAGE DIMENSIONS ChipFET] CASE 1206A−03 ISSUE G D 8 7 6 5 q L 5 6 3 7 2 8 1 HE 1 2 3 4 E 4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE. 4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL AND VERTICAL SHALL NOT EXCEED 0.08 MM. 5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS. 6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD SURFACE. DIM A b c D E e e1 L HE q STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. MILLIMETERS NOM MAX 1.05 1.10 0.30 0.35 0.15 0.20 3.05 3.10 1.65 1.70 0.65 BSC 0.55 BSC 0.28 0.35 0.42 1.80 1.90 2.00 5° NOM MIN 1.00 0.25 0.10 2.95 1.55 SOURCE 1 GATE 1 SOURCE 2 GATE 2 DRAIN 2 DRAIN 2 DRAIN 1 DRAIN 1 INCHES NOM 0.041 0.012 0.006 0.120 0.065 0.025 BSC 0.022 BSC 0.011 0.014 0.071 0.075 5° NOM MIN 0.039 0.010 0.004 0.116 0.061 MAX 0.043 0.014 0.008 0.122 0.067 e1 e b c A 0.05 (0.002) 0.017 0.079 ChipFET is a trademark of Vishay Siliconix. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arisi