UART Design and Application Considerations

www.DataSheet4U.com The NS16550A UART Design and Application Considerations The NS16550A UART Design and Application Considerations BACKGROUND UARTs like other system components have evolved for many years to become faster more integrated and less expensive The rise in popularity of the personal computer with its focus and competition primarily centered on an architecture introduced by IBM has driven both UART performance and software compatibility issues As transmission rates have increased the amount of time the CPU has for other tasks while handling an active serial channel has been sharply reduced One byte of data received at 1200 baud (8 3 ms) is received in th the time at 19 2 kbaud (520 ms) Software compatibility among the PC-based UARTs is critical due to the thousands of existing programs which use the serial channel and the new programs continually being offered Higher baud rates and compatibility requirements influence new UART designs These two constraints result in UARTs that are capable of higher data rates increasingly independent of CPU intervention and providing more autonomous features while maintaining software compatibility These development paths have been brought together in a new UART from National Semiconductor designated the NS16550A The NS16550A has all of the registers of its two predecessor parts (INS8250 and NS16450) so it can run all existing IBM PC XT AT RT and compatible serial port software In addition it has a programmable mode which incorporates new high-performance features Of course all of these advanced features are useful in any asynchronous serial communications application regardless of the host architecture The reader is assumed to be familiar with the standard features of the NS16450 so this paper will concentrate mainly on the new features of the NS16550A If the reader is unfamiliar with these UARTs it is advisable to start by reading their data sheets The first section reviews some of the design considerations and the operation of the NS16550A advanced features The second section shows an NS16550A initialization routine written in 80286 assembly code with an explanation of the routine The third section gives a detailed example of communications drivers written to interface two NS16550As on individual boards These drivers are written for use with National Semiconductor’s DB32032 evaluation boards but can be ported to any NS32032-based system containing an NS32202 (ICU) National Semiconductor Application Note 491 Martin S Michael Daniel G Durich July 1987 1 The CPU is usually much faster than the UART at transferring data A high speed CPU could transfer a byte of data to from the UART in a minimum of 280 ns The UART would take over 1800 times longer to transmit receive this data serially if it were operating at 19 2 kbaud There is a finite amount of wasted CPU time due to software overhead when stopping its current task to service the UART (context switching overhead) The CPU may be required to complete a certain portion of its current task in a multitasking system before servicing the UART This delay is the CPU latency time associated with servicing the interrupt The amount of time that the receiver can accept continuous data after it requests service from the CPU constrains CPU latency time 2 3 The design constraints listed above are met by adding two FIFOs and specialized transmitter receiver support circuitry to the existing NS16450 design The FIFOs are 16 bytes deep one holds data for the transmitter the other for the receiver (see Figure 1 ) Similarity between the FIFOs stops with their size as each has been customized for special TL C 9313 – 1 FIGURE 1 Rx and Tx FIFOs transmitter or receiver functions Each has support circuitry to minimize software overhead when handling interrupts The NS16550A receiver optimizes the CPU UART data transaction via the following features 1 The depth of the Receiver (Rx) FIFO ensures that as many as 16 characters will be ready to transfer when the CPU services the Rx interrupt Therefore the CPU transfer rate is effectively buffered from the serial data rate The program can select the number of bytes required in the Rx FIFO (1 4 8 or 14) before the UART issues an interrupt This allows the software to modify the interrupt trigger levels depending on its current task or loading It also ensures that the CPU doesn’t continually waste time switching context for only a few characters 1 0 Design Considerations and Operation of the New UART Features In order to optimize CPU UART data transactions the UART design takes into consideration the following constraints 2 AN-491 GNXTM is a trademark of National Semiconductor Corporation IBM is a registered trademark of International Business Machines Corporation VAXTM is a trademark of Digital Equipment Corporation 80286TM is a trademark of Intel Corporation C1995 National Semiconductor Corporation TL C 9313 RRD-B30M105 Printed in U S A www.DataSheet4U.com 3 The Rx FIFO will hold 16 bytes regardless of which trigger level the CPU selects This makes allowances for a variety of CPU latency times as the FIFO continues to fill after the interrupt is issued The NS16550A transmitter optimizes the CPU UART data transaction via the following features 1 The depth of the Transmitter (Tx) FIFO ensures that as many as 16 characters can be transferred when the CPU services the Tx interrupt Once again this effectively buffers the CPU transfer rate from the serial data rate The Transmitter (Tx) FIFO is similar in structure to FIFOs the user may have previously set up in RAM The Tx depth allows the CPU to load 16 characters each time it switches context to the service routine This reduces the impact of the CPU time lost in context switching Since a time lag in servicing an asynchronous transmitter usually has no penalty CPU latency time is of no concern to transmitter operation 2 data entering the Rx shift register will set the Overrun Error flag Normally the FIFO depth and the programmable trigger levels will give the CPU ample time to empty the Rx FIFO before an overrun occurs One side-effect of having a Rx FIFO is that the selected interrupt trigger level may be above the data level in the FIFO This could occur when data at the end of the block contains fewer bytes than the trigger level No interrupt would be issued to the CPU and the data would remain in the UART To prevent the software from having to check for this situation the NS16550A incorporates a timeout interrupt The timeout interrupt is activated when there is at least one byte in the Rx FIFO and neither the CPU nor the Rx shift register has accessed the Rx FIFO within 4 character times of the last byte The timeout interrupt is cleared or reset when the CPU reads the Rx FIFO or another character enters it These FIFO related features allow optimization of CPU UART transactions and are especially useful given the higher baud rate capability (256 kbaud) However in order to eliminate most CPU interactions the UART provides DMA request signals Two DMA modes are supported singletransfer and multi-transfer These modes allow the UART to interface to higher performance DMA units which can interleave their transfers between CPU cycles or execute multiple byte transfers In single-transfer mode the receiver DMA request signal (Rx RDY) goes active whenever there is at least one character in the Rx FIFO It goes inactive when the Rx FIFO is empty The transmitter DMA request signal (Tx RDY) goes active when there are no characters in the Tx FIFO It goes inactive when there is at least one character in the Tx FIFO Therefore in single-transfer mode active and inactive DMA signals are issued on a one byte basis In multi-transfer mode Rx RDY goes active whenever the trigger level or the timeout has been reached It goes inactive when the Rx FIFO is empty Tx RDY goes active when there is at least one unfilled position in the Tx FIFO It goes inactive when the Tx FIFO is completely full Therefore in multi-transfer mode active and inactive DMA signals are issued as the FIFO fills and empties With 2 DMA channels (one for each Rx and Tx) assigned to it the NS16550A could run somewhat independently of the CPU when the DMA unit transfers data composed of blocks with checksums SYSTEM OPERATION THE NS16550A VS THE NS16450 Consider the typical system interface block diagram in Figure 2 This is a simple diagram but it includes all of the components that typically interact with a UART The advantages of the NS16550A over the NS16450 can be illustrated by comparing some of the system constraints when each UART is substituted into this basic system Both RS-232C and RS-422A interfaces can be used with either UART however the NS16550A can drive these interfaces up to 256 kbaud Regarding the RS-422A specifica- 3 TX AND RX FIFO OPERATION The Tx portion of the UART transmits data through SOUT as soon as the CPU loads a byte into the Tx FIFO The UART will prevent loads to the Tx FIFO if it currently holds 16 characters Loading to the Tx FIFO will again be enabled as soon as the next character is transferred to the Tx shift register These capabilities account for the largely autonomous operation of the Tx The UART starts the above operations typically with a Tx interrupt The NS16550A issues a Tx interrupt whenever the Tx FIFO is empty and the Tx interrupt is enabled except in the following instance Assume that the Tx FIFO is empty and the CPU starts to load it When the first byte enters the FIFO the Tx FIFO empty interrupt will transition from active to inactive Depending on the execution speed of the service routine software the UART may be able to transfer this byte from the FIFO to the shift register before the CPU loads another byte If this happens the Tx FIFO will be empty again and typically the UART’s interrupt line would transition to the active state This could cause a system with an interrupt control unit to record a Tx FIFO empty condition even though