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www.DataSheet4U.com Accessing the NS16550A UART in the PS 2 Model 50 60 70 and 80 Accessing the NS16550A UART in the PS 2 Model 50 60 70 and 80 INTRODUCTION This paper reviews fundamental concepts of the Micro Channel Architecture and their relation to the NS16550A UART All 4 of the PS 2 personal computers reviewed use the NS16550A for asynchronous serial communication The first part is an overview of the PS 2 system board and Micro Channel Architecture (MCA) in the Models 50 60 70 and 80 personal computers The next part explains the basic configuration and system initialization procedures for the UART that occur after power-up The last part describes the overall interrupt procedure and the advantages of using the on-chip FIFOs of the NS16550A These explanations describe the CPU accesses to the UART via MCA Timing diagrams in the appendix show these accesses to the UART OVERVIEW OF THE PS 2 MODEL 50 60 70 AND 80 SYSTEM ARCHITECTURE The block diagram indicates a number of identical functions that all system boards have (Figure 1) Each system CPU has an 8 channel DMA Controller and an optional math coprocessor associated with it via the local bus The DMA Controller emulates the dual 8237 DMA controllers found on the IBM AT Additionally this DMA Controller provides Extended and Virtual Mode operation These modes allow it to interface with various DMA slave devices and the CPU to dynamically select the arbitration level for 2 of the DMA channels A central arbitration point allows certain adapter cards and system peripherals to compete for DMA transfers These adapter cards must have the appropriate arbitration and DMA logic Buffers condition the bus signals from the system CPU and send them directly to the Micro Channel Interface These signals after further buffering reach the system memory and the system peripherals The system ROM on the Models 50 and 60 also interfaces via these buffers to the 80286 CPU In the Models 70 and 80 the 128 kbyte ROM interfaces via the local bus to the 80386 CPU The dynamic RAM is expandable on the system board or on adapter cards DMA controller addressing capability limits the total DRAM available on any of these systems to 16 Mbytes The maximum DRAM available on the various system boards is 1 Model 50 Type 1 e 1 Mbyte Type 2 e 2 Mbytes 2 Model 60 e 1 Mbyte 3 Model 70 Type 1 or Type 2 e 6 Mbytes 4 Model 80 Type 1 e 2 Mbytes Type 2 e 4 Mbytes Beyond the memory coprocessor and DMA there are a number of major peripheral functions resident on the system board These are 1 serial port (NS16550A) 2 video graphics controller National Semiconductor Application Note 628 Martin S Michael July 1989 3 diskette controller 4 parallel port 5 keyboard and pointing device controller 6 CMOS clock and configuration RAM 7 dual interrupt controllers (16 channels) 8 timer (3 channels) The configuration software for the serial port on the system board restricts the addressing of the NS16550A to COM1 and COM2 on the Models 50 60 70 and 80 Adapter card serial ports however may be assigned any 1 of the 8 base I O addresses Adding adapter cards extends the PS 2 functionality beyond the system board These cards plug into the Micro Channel Bus connectors and conform to the MCA protocols OVERVIEW OF THE MICRO CHANNEL ARCHITECTURE MCA functionality increases as the data bus width increases from 16 to 32 bits Both bus widths support certain fundamental features regardless of the data bus width One of these is a centralized arbitration controller that allows up to 16 devices to contend for the 8 available DMA channels These devices compete based on an assigned priority level for the DMA resource A ‘‘fairness’’ option allows lower priority devices to compete successfully for a DMA channel even though higher priority devices may require a transfer If the fairness option is enabled each device that has received DMA service must wait until all other devices requesting the DMA have been serviced before they are allowed to compete for the DMA resource again MCA fixes the priority levels of the DMA channels except for channels 0 and 4 which the CPU can program to any priority level The DMA channels are capable of both 8- and 16-bit transfers MCA also features level sensitive interrupts provides for interrupt sharing and brings 11 of the 16 hardware interrupts out to the Micro Channel Bus for the adapters to use The last section of this paper describes interrupt handling in more detail Previous PC architectures used jumpers and switches to configure the adapter cards MCA uses programmable configuration registers on each adapter card instead This adds to system flexibility by allowing automatic card configuration via software The Models 50 and 60 support 8- or 16-bit transfers over a 64 kbyte range of I O addresses and over a 16 Mbyte range of memory addresses The Models 70 and 80 have all of these capabilities and can execute 32-bit transfers over the 64 kbyte I O address range or the 4 Gbyte memory address range AN-628 IBM PC PS 2 and MicroChannel are registered trademarks of International Business Machines Corporation TL C 10456 RRD-B30M75 Printed in U S A C1995 National Semiconductor Corporation www.DataSheet4U.com TL C 10456 – 1 FIGURE 1 PS 2 Block Diagram TL C 10456 – 2 FIGURE 2 Micro Channel Architecture 2 www.DataSheet4U.com SUBDIVIDING THE MICRO CHANNEL ARCHITECTURE MCA has an 8-bit core set of bus signals (Figure 2) and 4 types of extensions If the system CPU is an 80286 a 16-bit extension and an auxiliary video extension are present If the system CPU is an 80386 a 32-bit extension and a Matched Memory extension are present in addition to the 16-bit and auxiliary video extensions The 8-bit core set of 90 signals are composed of 9 groups Most of these are the typical bus signals associated with any CPU 24 address 8 data 14 control 6 interrupts 9 power IBM reserved four 14 ground 8 DMA arbitration 2 audio a 14 3 MHz clock signal signals in this set In summary the MCA provides all signals necessary for CPU or DMA data transfer to additional memory and peripherals and for monitoring card or bus status It also supports some miscellaneous functions (e g audio more interrupts a clock oscillator etc ) The four extensions provide for data bus expansion to 32 bits fast memory access and auxiliary video control OVERVIEW OF THE PROGRAMMABLE OPTION SELECT (POS) The Models 50 60 70 and 80 use software to configure the system peripherals and adapter cards rather than providing switches and jumpers This software is called the Configuration Utilities These utilities match the system peripherals and adapter cards to their appropriate initialization files The initialization files are known as Adapter Description Files (ADFs) These files each have an I D number that associates each ADF with the matching adapter card I D number The ADF contains specific information used by the operator during system configuration such as the adapter card name the system resources the adapter can use and help information It indicates to the system the minimum resources required for the adapter card to run It also contains the codes used to record the specific options chosen by the operator (e g one of the options for an asynchronous communication card is the assignment of the COM port number to each UART) The ADF will specify the interrupt level the arbitration level the I O register addresses and the memory range addresses of the adapter card The Configuration Utilities use this information to configure the adapter card and provide selectable options to the operator ADFs are ASCII files When invoked the Configuration Utilities begin reading the adapter card I D numbers and then read the ADF I D numbers (Figure 3) They disable any cards that don’t have an ADF and indicate any conflict of resources (e g the same COM port address assigned to two different UARTs) to the operator When there are no conflicts or when the system is automatically configured the utilities generate the system configuration data The 64-byte CMOS RAM (all models) and the 2 kbyte CMOS RAM extension (Model 60 70 and 80) store the configuration data Once stored the system is ready for normal power-up operation During normal power-up (Figure 4) the Power On Self-Test (POST) software tests the hardware and compares the adapter I D numbers to those in the configuration RAM If the numbers match it initializes each adapter card If they don’t match it requests that the Configuration Utilities be run to resolve the conflicts UART ACCESSES SOFTWARE During normal operation UART accesses are done by the applications software via DOS routines BIOS routines or by direct access to the UARTs designated addresses The addresses of each UART in the system are assigned during system configuration Using the Configuration Utilities the operator assigns 1 of 8 available base addresses to the asynchronous communications ports on the adapter cards Table 1 lists all possible addresses for the asynchronous communications ports they include the original ‘‘COM1’’ and ‘‘COM2’’ addresses of the IBM AT in order to maintain software compatibility The 14 control signals can be grouped by function A typical data transfer uses 7 The bus master uses 4 to sense card and channel status Reset and channel configuration require 2 and a DRAM refresh cycle activates 1 signal The centralized arbitration controller uses 8 DMA arbitration signals to support its features plus the facility for single or burst mode transfers One signal notifies the DMA slave when the DMA channel it is using reaches its terminal count An audio summation input is available with a separate audio ground so that all cards can drive the speaker Power and ground pin spacing keeps all bus signals within 0 1 inch of an AC ground potential thus minimizing EMI This core set of signals provides the fundamental structure of MCA Four extensions contain the remaining MCA Bus signals The 16-bit Extension widens the