2.5V/3.3V SiGe Differential Smart Gate

NBSG86A 2.5V/3.3V SiGe Differential Smart Gate with Output Level Select The NBSG86A is a multi−function differential Logic Gate which can be configured as an AND/NAND, OR/NOR, XOR/XNOR, or 2:1 MUX. This device is part of the GigaComm™ family of high performance Silicon Germanium products. The device is housed in a low profile 4x4 mm, 16−pin, flip−chip BGA or a 3x3 mm 16 pin QFN package. Differential inputs incorporate internal 50 W termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), LVCMOS/LVTTL, CML, or LVDS. The OLS* input is used to program the peak−to−peak output amplitude between 0 and 800 mV in five discrete steps. The NBSG86A employs input default circuitry so that under open input conditions (Dx, Dx, VTDx, VTDx, VTSEL) the outputs of the device will remain stable. Features http://onsemi.com MARKING DIAGRAM* FCBGA−16 BA SUFFIX CASE 489 16 1 SG 86A LYW 1 QFN−16 MN SUFFIX CASE 485G • Maximum Input Clock Frequency > 8 GHz Typical • • • • Maximum Input Data Rate > 8 Gb/s Typical 165 ps Typical Propagation Delay 40 ps Typical Rise and Fall Times www.DataSheet4U.com Selectable Swing PECL Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V • Selectable Swing NECL Output with NECL Inputs with Operating Range: VCC = 0 V with VEE = −2.375 V to −3.465 V • Selectable Output Level (0 V, 200 mV, 400 mV, 600 mV, or 800 mV Peak−to−Peak Output) • 50 W Internal Input Termination Resistors A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. • Pb−Free Packages are Available *Output Level Select ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. © Semiconductor Components Industries, LLC, 2006 1 July, 2006 − Rev. 10 Publication Order Number: NBSG86A/D ÇÇ ÇÇ SG 86A ALYWG G NBSG86A 1 A VTD1 2 D1 3 D1 4 VTD1 VTD0 D0 16 OLS 15 D0 14 VTD0 13 Exposed Pad (EP) 12 11 VEE Q Q VCC 1 2 NBSG86A 3 4 B SEL VTSEL VCC Q SEL Q C SEL OLS VEE SEL VTSEL 10 9 D VTD0 D0 D0 VTD0 5 VTD1 6 D1 7 8 D1 VTD1 Figure 1. BGA−16 Pinout (Top View) Table 1. Pin Description Pin BGA C2 C1 QFN 1 2 Name OLS (Note 3) SEL I/O Input ECL, CML, LVCMOS, LVDS, LVTTL Input ECL, CML, LVCMOS, LVDS, LVTTL Input − − ECL, CML, LVCMOS, LVDS, LVTTL Input ECL, CML, LVCMOS, LVDS, LVTTL Input − − RSECL Output RSECL Output − − ECL, CML, LVCMOS, LVDS, LVTTL Input ECL, CML, LVCMOS, LVDS, LVTTL Input − − Figure 2. QFN−16 Pinout (Top View) Description Input Pin for the Output Level Select (OLS). See Table 2. Inverted Differential Select Logic Input. B1 3 SEL Noninverted Differential Select Logic Input. B2 A1 A2 4 5 6 VTSEL VTD1 D1 Common Internal 50 W Termination Pin for SEL/SEL. See Table 7. (Note 1) Internal 50 W termination pin. See Table 7. (Note 1) Noninverted Differential Input 1. Internal 75 kW to VEE. A3 7 D1 Inverted Differential Input 1. Internal 75 kW to VEE and 36.5 kW to VCC. A4 B3 B4 C4 C3 D4 D3 8 9 10 11 12 13 14 VTD1 VCC Q Q VEE VTD0 D0 Internal 50 W Termination Pin. See Table 7. (Note 1) Positive Supply Voltage (Note 2) Noninverted Differential Output. Typically Terminated with 50 W Resistor to VTT = VCC − 2 V. Inverted Differential Output. Typically Terminated with 50 W Resistor to VTT = VCC − 2 V Negative Supply Voltage (Note 2) Internal 50 W Termination Pin. See Table 7. (Note 1) Inverted Differential Input 0. Internal 75 kW to VEE and 36.5 kW to VCC. D2 15 D0 Noninverted Differential Input 0. Internal 75 kW to VEE. D1 N/A 16 − VTD0 EP Internal 50 W Termination Pin. See Table 7. (Note 1) Exposed Pad. The thermally exposed pad on package bottom (see case drawing) must be attached to a heat−sinking conduit. 1. In the differential configuration when the input termination pins (VTDx, VTDx, VTSEL) are connected to a common termination voltage, and if no signal is applied then the device will be susceptible to self−oscillation. 2. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. 3. When an output level of 400 mV is desired and VCC − VEE > 3.0 V, 2 kW resistor should be connected from OLS pin to VEE. http://onsemi.com 2 NBSG86A Table 2. OUTPUT LEVEL SELECT OLS OLS VCC VCC − 0.4 V VCC − 0.8 V VCC − 1.2 V VEE (Note 4) Float Q/Q VPP 800 mV 200 mV 600 mV 0 400 mV 600 mV OLS Sensitivity OLS − 75 mV OLS $ 150 mV OLS $ 100 mV OLS $ 75 mV OLS $ 100 mV N/A 4. When an output level of 400 mV is desired and VCC − VEE > 3.0 V, 2.0 kW resistor should be connected from OLS to VEE. 50 W VTD0 D0 R1 D0 VTD0 50 W 50 W VTD1 D1 R1 D1 VTD1 50 W VTSEL SEL SEL R1 R2 50 W 50 W R1 Q Q R2 Figure 3. Logic Diagram 50 W VTD0 VT or VBB VCC VTD0 VTD1 50 W 50 W D0 D0 Q Q D1 D1 VTD1 50 W 50 W 50 W VEE VCC SEL D0 0 0 0 0 Table 3. AND/NAND TRUTH TABLE (Note 5) m D1 0 0 1 1 b SEL 0 1 0 1 m*b Q 0 0 0 1 m 5. D0, D1, SEL are inverse of D0, D1, SEL unless specified otherwise. VTSEL SEL b Figure 4. Configuration for AND/NAND Function http://onsemi.com 3 NBSG86A 50 W VTD0 m VTD0 50 W 50 W VTD1 VCC VT or VBB VTD1 50 W D0 D0 Q Q D1 D1 50 W 50 W Table 4. OR/NOR TRUTH TABLE** m D0 0 0 1 1 D1 1 1 1 1 b SEL 0 1 0 1 m or b Q 0 1 1 1 ** D0, D1, SEL are inverse of D0, D1, SEL unless specified otherwise. VTSEL SEL b SEL Figure 5. Configuration for OR/NOR Function 50 W VTD0 m VTD0 50 W 50 W VTD1 D0 D0 Q Q D1 D1 Table 5. XOR/XNOR TRUTH TABLE** m D0 0 0 1 50 W 1 D1 1 1 0 0 b SEL 0 1 0 1 m XOR b Q 0 1 1 0 VTD1 50 W 50 W VTSEL SEL ** D0, D1, SEL are inverse of D0, D1, SEL unless specified otherwise. SEL b Figure 6. Configuration for XOR/XNOR Function 50 W VTD0 D0 D0 VTD0 50 W 50 W VTD1 D1 D1 VTD1 50 W 50 W 50 W Q Q Table 6. 2:1 MUX TRUTH TABLE** SEL 1 0 Q D1 D0 ** D0, D1, SEL are inverse of D0, D1, SEL unless specified otherwise. VTSEL SEL SEL Figure 7. Configuration for 2:1 MUX Function http://onsemi.com 4 NBSG86A Table 7. Interfacing Options INTERFACING OPTIONS CML LVDS AC−COUPLED RSECL, PECL, NECL LVTTL, LVCMOS CONNECTIONS Connect VTD0, VTD1, VTSEL and VTD0, VTD1 to VCC Connect VTD0, VTD1, VTD0 and VTD1 together. Leave VTSEL open. Bias VTD0, VTD1, VTSEL and VTD0, VTD1 Inputs within (VIHCMR) Common Mode Range Standard ECL Termination Techniques An external voltage should be applied to the unused complementary differential input. Nominal voltage 1.5 V for LVTTL and VCC/2 for LVCMOS inputs. Table 8. ATTRIBUTES Characteristics Internal Input Pulldown Resistors Internal Input Pullup Resistor ESD Protection (R1) (R2) Human Body Model Machine Model Charged Device Model 16−FCBGA 16−QFN Oxygen Index: 28 to 34 Value 75 kW 37.5 kW > 1 KV > 50 V > 4 KV Level 3 Level 1 UL 94 V−0 @ 0.125 in 364 Moisture Sensitivity (Note 6) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 6. For additional information, see Application Note AND8003/D. Table 9. MAXIMUM RATINGS (Note 7) Symbol VCC VEE VI VINPP IIN Iout TA Tstg qJA Parameter Positive Power Supply Negative Power Supply Positive Input Negative Input Differential Input Voltage |Dn − Dn| Input Current Through RT (50 W Resistor) Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction−to−Ambient) (Note 8) 0 LFPM 500 LFPM 0 LFPM 500 LFPM 2S2P (Note 8) 2S2P (Note 9) < 15 sec < 3 sec @ 248°C < 3 sec @ 260°C 16 FCBGA 16 FCBGA 16 QFN 16 QFN 16 FCBGA 16 QFN Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V VCC − VEE w 2.8 V VCC − VEE < 2.8 V Static Surge Continuous Surge 16−FCBGA 16−QFN VI v VCC VI w VEE Condition 2 Rating 3.6 −3.6 3.6 −3.6 2.8 |VCC − VEE| 45 80 25 50 −40 to +70 −40 to +85 −65 to +150 108 86 41.6 35.2 5.0 4.0 225 265 265 Units V V V V V V mA mA mA mA °C °C °C °C/W °C/W °C/W °C/W °C/W °C/W °C qJC Tsol Thermal Resistance (Junction−to−Case) Wave Solder Pb (BGA) Pb (QFN) Pb−Free (QFN) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 7. Maximum Ratings are those values beyond which device damage may occur. 8. JEDEC standard multilayer board − 2S2P (2 signal, 2 power). 9. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 5 NBSG86A Table 10. DC CHARACTERISTICS, INPUT WITH PECL OUTPUT VCC = 2.5 V; VEE = 0 V (Note 10) −40°C Symbol IEE VOH VOL Characteristic Negative Power Supply Current Output HIGH Voltage (Note 11) Output LOW Voltage (Note 11) (OLS = VCC) (OLS = VCC − 0.4 V) (OLS = VCC − 0.8 V, OLS = FLOAT) (OLS = VCC − 1.2 V) (OLS = VEE) Output Voltage Amplitude (OLS = VCC) (OLS = VCC − 0.4 V) (OLS = VCC − 0.8 V, OLS = FLOAT) (OLS = VCC − 1.2 V) (OLS = VEE) VIH VIL VIHCMR Input HIGH Voltage (Single−Ended) (Note 13) D, D Input LOW Voltage (Single−Ended) (Note 14) D, D Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 12) Internal Input Termination Resistor Input HIGH Current (@VIH) Input LOW Current (@VIL) D, D SEL D, D SEL 670 125 510 0 325 VEE + 1275 VEE 1.2 800 215 615 5 415 VCC − 1000* VCC− 1400* VCC VIH− 150 2.5 660 120 505 0 320 VEE + 1275 VEE 1.2 795 210 610 0 410 VCC − 1000* VCC− 1400* VCC VIH− 150 2.5 655 120 500 0 320 VEE + 1275 VEE 1.2 790 210 605 5 410 VCC− 1000* VCC− 1400* VCC VIH− 150 2.5 mV mV V Min 23 1460 555 1235 775 1455 1005 Typ 30 1510 705 1295 895 1505 1095 Max 39 1560 855 1385 1015 1585 1215 Min 23 1490 595 1270 810 1490 1040 25°C Typ 30 1540 745 1330 930 1540 1130 Max 39 1590 895 1420 1050 1620 1250 70°C(BGA)/85°C(QFN)** Min 23 1515 625 1295 840 1510 106