2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider

NBSG53A 2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip−Flop/Clock Divider with Reset and OLS* The NBSG53A is a multi−function differential D flip−flop (DFF) or fixed divide by two (DIV/2) clock generator. This is a part of the GigaComm™ family of high performance Silicon Germanium products. A strappable control pin is provided to select between the two functions. The device is housed in a low profile 4x4 mm 16−pin Flip−Chip BGA (FCBGA) or a 3x3 mm 16 pin QFN package. The NBSG53A is a device with data, clock, OLS*, reset, and select inputs. Differential inputs incorporate internal 50 W termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), LVCMOS/LVTTL, CML, or LVDS. The OLS* input is used to program the peak−to−peak output amplitude between 0 and 800 mV in five discrete steps. The RESET and SELECT inputs are single−ended and can be driven with either LVECL or LVCMOS/LVTTL input levels. Data is transferred to the outputs on the positive edge of the clock. The differential clock inputs of the NBSG53A allow the device to also be used as a negative edge triggered device. Features www.DataSheet4U.com http://onsemi.com MARKING DIAGRAM** FCBGA−16 BA SUFFIX CASE 489 SG 53A LYW 1 1 QFN−16 MN SUFFIX CASE 485G • Maximum Input Clock Frequency (DFF) > 8 GHz Typical • Maximum Input Clock Frequency (DIV/2) > 10 GHz Typical • • • • • (See Figures 5, 7, 9, 10, and 11) 210 ps Typical Propagation Delay (OLS = FLOAT) 45 ps Typical Rise and Fall Times (OLS = FLOAT) DIV/2 Mode (Active with Select Low) DFF Mode (Active with Select High) (See Figures 4, 6, 8, 10, and 11) A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 16 of this data sheet. Selectable Swing PECL Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V • Selectable Swing NECL Output with NECL Inputs with Operating Range: VCC = 0 V with VEE = −2.375 V to −3.465 V • Selectable Output Level (0 V, 200 mV, 400 mV, 600 mV, or 800 mV Peak−to−Peak Output) • 50 W Internal Input Termination Resistors on all Differential Inputs • Pb−Free Packages are Available *Output Level Select © Semiconductor Components Industries, LLC, 2006 1 July, 2006 − Rev. 8 Publication Order Number: NBSG53A/D ÇÇ ÇÇ 16 SG 53A ALYWG G NBSG53A 1 A VTD 2 D 3 D 4 VTD VCC 16 VTCLK R 15 SEL OLS 14 13 Exposed Pad (EP) 12 11 VEE Q Q VCC 1 2 NBSG53A 3 4 5 VTD 6 D 7 D 8 VTD B CLK VTCLK VCC Q CLK Q C CLK VTCLK VEE CLK VTCLK 10 9 D VCC R SEL OLS Figure 1. BGA−16 Pinout (Top View) Table 1. Pin Description Pin BGA C2 C1 QFN 1 2 Name VTCLK CLK I/O − ECL, CML, LVCMOS, LVDS, LVTTL Input ECL, CML, LVCMOS, LVDS, LVTTL Input − − ECL, CML, LVCMOS, LVDS, LVTTL Input ECL, CML, LVCMOS, LVDS, LVTTL Input − − RSECL Output RSECL Output − Input LVECL, LVCMOS, LVTTL Input LVECL, LVCMOS, LVTTL Input Figure 2. QFN−16 Pinout (Top View) Description Internal 50 W Termination Pin. See Table 4. Inverted Differential Input. B1 3 CLK Noninverted Differential Input. B2 A1 A2 4 5 6 VTCLK VTD D Internal 50 W Termination Pin. See Table 4. Internal 50 W termination pin. See Table 4. Inverted Differential Input. A3 7 D Noninverted Differential Input. A4 D1,B3 B4 C4 C3 D4 D3 8 9,16 10 11 12 13 14 VTD VCC Q Q VEE OLS* SEL Internal 50 W Termination Pin. See Table 4. Positive Supply Voltage NonInverted Differential Output. Typically Terminated with 50 W Resistor to VTT = VCC − 2 V. Inverted Differential Output. Typically Terminated with 50 W Resistor to VTT = VCC − 2 V. Negative Supply Voltage Input Pin for the Output Level Select (OLS). See Table 2. Select Logic Input. Internal 75 kW to VEE. D2 15 R Reset D Flip−Flop. Internal 75 kW to VEE. N/A − EP Exposed Pad. (Note 1) 1. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad (EP) on package bottom (see case drawing) must be attached to a heat−sinking conduit. 2. In the differential configuration when the input termination pins (VTD, VTD, VTCLK, VTCLK) are connected to a common termination voltage, and if no signal is applied then the device will be susceptible to self−oscillation. 3. When an output level of 400 mV is desired and VCC − VEE > 3.0 V, 2KW resistor should be connected from OLS pin to VEE. http://onsemi.com 2 NBSG53A VCC OLS VTD 50 W D D 50 W VTD 2 2 D Flip−Flop (DFF) R 2 2 VTCLK 50 W CLK CLK 50 W VTCLK R SEL 75 kW 75 kW 2 R Q D Flip−Flop (DIV/2) Q 2 1 0 2 Q Q VEE Figure 3. Simplified Logic Diagram Table 2. OUTPUT LEVEL SELECT (OLS) OLS VCC VCC − 0.4 V VCC − 0.8 V VCC − 1.2 V VEE (Note 4) Float Q/Q VPP 800 mV 200 mV 600 mV 0 400 mV 600 mV OLS Sensitivity OLS − 75 mV OLS $ 150 mV OLS $ 100 mV OLS $ 75 mV OLS + 100 mV N/A Table 3. TRUTH TABLE R H L L L SEL x H H L D x L H x CLK x Z Z Z Q L L H Q Function Reset DFF DFF DIV/2 Z = LOW to HIGH Transition 4. When an output level of 400 mV is desired and VCC − VEE > 3.0 V, 2.0 kW resistor should be connected from OLS to VEE. Table 4. INTERFACING OPTIONS INTERFACING OPTIONS CML LVDS AC−COUPLED RSECL, PECL, NECL LVTTL, LVCMOS CONNECTIONS Connect VTCLK, VTD and VTCLK, VTD to VCC Connect VTCLK, VTD and VTCLK, VTD Together Bias VTCLK, VTD and VTCLK, VTD Inputs within Common Mode Range (VIHCMR) Standard ECL Termination Techniques An External Voltage (VTHR) should be Applied to the Unused Complementary Differential Input. Nominal VTHR is 1.5 V for LVTTL and VCC/2 for LVCMOS Inputs. This Voltage must be within the VTHR Specification. http://onsemi.com 3 NBSG53A Table 5. ATTRIBUTES Characteristics Positive Operating Voltage Range for VCC (VEE = 0 V) Negative Operating Voltage Range for VEE (VCC = 0 V) Internal Input Pulldown Resistor (R, SEL) ESD Protection Human Body Model Machine Model Charged Device Model 16−FCBGA 16−QFN Value 2.375 V to 3.465 V −2.375 V to −3.465 V 75 kW > 1.5 kV > 50 V > 4 kV Level 3 Level 1 UL 94 V−0 @ 0.125 in 28 to 34 482 Moisture Sensitivity (Note 5) Flammability Rating Oxygen Index Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 5. For additional information, refer to Application Note AND8003/D. Table 6. MAXIMUM RATINGS Symbol VCC VEE VI VINPP IIN IOUT TA Tstg qJA Parameter Positive Power Supply Negative Power Supply Positive Input Negative Input Differential Input Voltage |D − D| Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V VCC − VEE w 2.8 V VCC − VEE < 2.8 V Static Surge Continuous Surge 16 FCBGA 16 QFN VI v VCC VI w VEE Condition 2 Rating 3.6 −3.6 3.6 −3.6 2.8 |VCC − VEE| 45 80 25 50 −40 to +70 −40 to +85 −65 to +150 0 LFPM 500 LFPM 0 LFPM 500 LFPM 2S2P (Note 6) 2S2P (Note 7) < 15 sec < 3 sec @ 248°C < 3 sec @ 260°C 16 FCBGA 16 FCBGA 16 QFN 16 QFN 16 FCBGA 16 QFN 108 86 41.6 35.2 5.0 4.0 225 265 265 Units V V V V V V mA mA mA mA °C °C °C/W °C/W °C/W °C/W °C/W °C/W °C Input Current Through RT (50 W Resistor) Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction−to−Ambient) (Note 6) qJC Tsol Thermal Resistance (Junction−to−Case) Wave Solder Pb (BGA) Pb (QFN) Pb−Free (QFN) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 6. JEDEC standard 51−6, multilayer board − 2S2P (2 signal, 2 power). 7. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 4 NBSG53A Table 7. DC CHARACTERISTICS, INPUT WITH PECL OUTPUT VCC = 2.5 V; VEE = 0 V (Note 8) −40°C Symbol IEE VOH VOL Characteristic Negative Power Supply Current Output HIGH Voltage (Note 9) Output LOW Voltage (Note 9) (OLS = VCC) (OLS = VCC − 0.4 V) (OLS = VCC − 0.8 V, OLS = FLOAT) (OLS = VCC − 1.2 V) (OLS = VEE) Output Voltage Amplitude (OLS = VCC) (OLS = VCC − 0.4 V) (OLS = VCC − 0.8 V, OLS = FLOAT) (OLS = VCC − 1.2 V) (OLS = VEE) VIH VIL VIH VIL VTHR VIHCMR Input HIGH Voltage (Single−Ended) (Notes 11 and 13) CLK, CLK, D, D Input LOW Voltage (Single−Ended) (Notes 12 and 13) CLK, CLK, D, D Input High Voltage (Single−Ended) R, SEL Input Low Voltage (Single−Ended) R, SEL Input Threshold Voltage (Single−Ended) (Note 13) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 10) Internal Input Termination Resistor Input HIGH Current (@VIH) R, SEL CLK, CLK, D, D Input LOW Current (@VIL) R, SEL CLK, CLK, D, D 670 125 510 0 325 VEE + 1275 VEE 800 215 615 5 415 VCC − 1000* VCC− 1400* VCC VIH− 150 VCC 890 VCC− 75 2.5 660 120 505 0 320 VEE + 1275 VEE 795 210 610 0 410 VCC − 1000* VCC− 1400* VCC VIH− 150 VCC 955 VCC− 75 2.5 655 120 500 0 320 VEE + 1275 VEE 790 210 605 5 410 VCC− 1000* VCC− 1400* VCC VIH− 150 VCC mV VEE VEE+ 1125 1.2 VEE VEE+ 1125 1.2 VEE VEE+ 1125 1.2 1015 VCC− 75 2.5 mV V mV mV mV 1290 1355 1415 Min 33 1460 555 1235 775 1455 1005 Typ 45 1510 705 1295 895 1505 1095 Max 57 1560 855 1385 1015 1585 1215 Min 33 1490 595 1270 810 1490 1040 25°C Typ 45 1540 745 1330 930 1540 1130 Max 57 1590 895 1420 1050 1620 1250 70°C(BGA)/85°C(QFN)** Min 33 1515 625 1295 840 1510 1065 Typ 45 1565 775 1355 960 1560 1155 Max 57 1615 925 1445 1080 1640 1275 mV Unit mA mV mV VOUTPP RTIN IIH IIL 45 50 35 5 20 5 55 100 50 100 50 45 50 35 5 20 5 55 100 50 100 50 45 50 35 5 20 5 55 100 50 100 50 W mA mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed cir