2.5V/3.3V SiGe Differential Receiver/Driver

NBSG16VS 2.5V/3.3V SiGe Differential Receiver/Driver with Variable Output Swing Description 1 QFN−16 MN SUFFIX CASE 485G Features • • • • • • • • • • • Maximum Input Clock Frequency up to 12 GHz Typical Maximum Input Data Rate up to 12 Gb/s Typical 40 ps Typical Rise and Fall Times (VCTRL = VCC − 1 V) 120 ps Typical Propagation Delay (VCTRL = VCC − 1 V) Variable Swing PECL Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V Variable Swing NECL Output with NECL Inputs with Operating Range: VCC = 0 V with VEE = −2.375 V to −3.465 V Output Level (100 mV to 750 mV Peak−to−Peak Output; VCC − VEE = 3.0 V to 3.465 V), Differential Output Only 50 W Internal Input Termination Resistors Compatible with Existing 2.5 V/3.3 V EP Devices VBB and VMM Reference Voltage Output Pb−Free Packages are Available A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. © Semiconductor Components Industries, LLC, 2006 1 July, 2006 − Rev. 7 Publication Order Number: NBSG16VS/D ÇÇ ÇÇ The NBSG16VS is a differential receiver/driver targeted for high frequency applications that require variable output swing. The device is functionally equivalent to the EP16VS device with much higher bandwidth and lower EMI capabilities. This device may be used for applications driving VCSEL lasers. Inputs incorporate internal 50 W termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), LVTTL, LVCMOS, CML, or LVDS. The output amplitude is varied by applying a voltage to the VCTRL input pin. Outputs are variable swing ECL from 100 mV to 750 mV amplitude, optimized for operation from VCC − VEE = 3.0 V to 3.465 V. The VBB and VMM pins are internally generated voltage supplies available to this device only. The VBB is used as a reference voltage for single−ended NECL or PECL inputs and the VMM pin is used as a reference voltage for LVCMOS inputs. For single−ended input operation, the unused complementary differential input is connected to VBB or VMM as a switching reference voltage. VBB or VMM may also rebias AC coupled inputs. When used, decouple VBB and VMM via a www.DataSheet4U.com 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB and VMM outputs should be left open. http://onsemi.com MARKING DIAGRAMS* SG 11 ALYW FCBGA−16 BA SUFFIX CASE 489 16 SG 16VS ALYWG G NBSG16VS 1 A VEE 2 NC 3 VCTRL 4 VEE VEE 16 VTD VBB VMM 15 14 VEE 13 Exposed Pad (EP) 1 2 NBSG16VS 3 4 12 11 10 9 VCC Q Q VCC B D VTD VCC Q D Q C D VTD VCC D VTD D VEE VBB VMM VEE 5 VEE 6 7 8 NC VCTRL VEE Figure 1. BGA−16 Pinout (Top View) Figure 2. QFN−16 Pinout (Top View) Table 1. PIN DESCRIPTION Pin BGA C2 C1 QFN 1 2 Name VTD D I/O − ECL, CML, LVCMOS, LVDS, LVTTL Input ECL, CML, LVCMOS, LVDS, LVTTL Input − − − Description Internal 50 W Termination Pin. See Table 2. Inverted Differential Input. Internal 75 kW to VEE and 36.5 kW to VCC. B1 3 D Noninverted Differential Input. Internal 75 kW to VEE. B2 A1,D1,A4, D4 A2 A3 B3,C3 B4 C4 D3 D2 N/A 4 5,8,13,16 6 7 9,12 10 11 14 15 − VTD VEE NC VCTRL VCC Q Q VMM VBB EP Internal 50 W Termination Pin. See Table 2. Negative Supply Voltage No Connect Output Amplitude Swing Control. Bypass Pin to VCC through 0.1 mF Capacitor. − RSECL Output RSECL Output − − − Positive Supply Voltage Noninverted Differential Output. Typically Terminated with 50 W to VTT = VCC − 2 V Inverted Differential Output. Typically Terminated with 50 W to VTT = VCC − 2 V LVCMOS Reference Voltage Output. (VCC − VEE)/2 ECL Reference Voltage Output Exposed Pad. (Note 2) 1. The NC pin is electrically connected to the die and must be left open. 2. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad on package bottom (see case drawing) must be attached to a heat−sinking conduit. 3. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage, and if no signal is applied then the device will be susceptible to self−oscillation. http://onsemi.com 2 NBSG16VS VCC + VCTRL 0.1 mF VCTRL VTD 50 W D D Q 50 W VTD 75 KW 75 KW VBB VCC − 2 V VEE VEE 50 W 50 W VTD VCC 36.5 KW Q Q OUT Q OUT VMM VTD 50 W D D 50 W 75 KW 75 KW Q 140 W VBB 140 W 36.5 KW Q Q OUT Q OUT VMM RVAR VCTRL VCC +3.3 V Figure 3. Logic Diagram/ Voltage Source Implementation Figure 4. Alternative Voltage Source Implementation Table 2. INTERFACING OPTIONS INTERFACING OPTIONS CML LVDS AC−COUPLED RSECL, PECL, NECL LVTTL CONNECTIONS Connect VTD and VTD to VCC Connect VTD and VTD Together Bias VTD and VTD Inputs within Common Mode Range (VIHCMR) Standard ECL Termination Techniques An external voltage should be applied to the unused complementary differential input. Nominal voltage is 1.5 V for LVTTL. VMM should be connected to the unused complementary differential input. LVCMOS http://onsemi.com 3 NBSG16VS Table 3. ATTRIBUTES Characteristics Internal Input Pulldown Resistor (D, D) Internal Input Pullup Resistor (D) ESD Protection Moisture Sensitivity (Note 4) FCBGA−16 QFN−16 Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 4. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34 Human Body Model Machine Model Pb Pkg Level 3 Level 1 Value 75 kW 36.5 kW > 2 kV > 100 V Pb−Free Pkg N/A Level 1 UL 94 V−0 @ 0.125 in 192 Table 4. MAXIMUM RATINGS Symbol VCC VEE VI VINPP IOUT IIN IBB IMM TA Tstg qJA Parameter Positive Power Supply Negative Power Supply Positive Input Negative Input Differential Input Voltage Output Current Input Current Through RT (50 W Resistor) VBB Sink/Source VMM Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction−to−Ambient) (Note 5) 0 lfpm 500 lfpm 0 lfpm 500 lfpm 2S2P (Note 5) 2S2P (Note 6) 16 FCBGA 16 FCBGA 16 QFN 16 QFN 16 FCBGA 16 QFN |D − D| Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V VCC − VEE w 2.8 V VCC − VEE t 2.8 V Continuous Surge Static Surge VI v VCC VI w VEE Condition 2 Rating 3.6 −3.6 3.6 −3.6 2.8 |VCC − VEE| 25 50 45 80 1 1 −40 to +85 −65 to +150 108 86 41.6 35.2 5.0 4.0 225 225 Unit V V V V V V mA mA mA mA mA mA °C °C °C/W °C/W °C/W °C/W °C/W °C/W °C qJC Tsol Thermal Resistance (Junction−to−Case) Wave Solder Pb Pb−Free Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 5. JEDEC standard 51−6 multilayer board − 2S2P (2 signal, 2 power). 6. JEDEC standards multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 4 NBSG16VS Table 5. DC CHARACTERISTICS, INPUT WITH VARIABLE PECL OUTPUT VCC = 2.5 V; VEE = 0 V (Note 7) −40°C Symbol IEE VOH VOL Characteristic Negative Power Supply Current Output HIGH Voltage (Note 8) Output LOW Voltage (Note 8) (Max Swing) (VCTRL = VCC − 600 mV) VIH VIL VBB VIHCMR Input HIGH Voltage (Single−Ended) (Notes 10 and 11) Input LOW Voltage (Single−Ended) (Notes 10 and 12) PECL Output Voltage Reference Input HIGH Voltage Common Mode Range (Note 9) (Differential Configuration) CMOS Output Voltage Reference (VCC − VEE)/2 Internal Input Termination Resistor Input HIGH Current (@ VIH) Input LOW Current (@ VIL) 645 1090 VTHR + 75 VIH − 2500 1080 1.2 765 1210 VCC − 1000* VCC − 1400* 1140 885 1330 VCC VTHR − 75 1200 2.5 605 1035 VTHR + 75 VIH − 2500 1080 1.2 725 1155 VCC − 1000* VCC − 1400* 1140 845 1275 VCC VTHR − 75 1200 2.5 600 1010 VTHR + 75 VIH − 2500 1080 1.2 720 1130 VCC − 1000* VCC − 1400* 1140 840 1250 VCC VTHR − 75 1200 2.5 mV mV mV V Min 18 1315 Typ 25 1440 Max 32 1565 Min 18 1305 25°C Typ 25 1430 Max 32 1555 Min 18 1305 85°C Typ 25 1430 Max 32 1555 Unit mA mV mV VMM RTIN IIH IIL mV 1100 45 1250 50 30 25 1400 55 100 50 1100 45 1250 50 30 25 1400 55 100 50 1100 45 1250 50 30 25 1400 55 100 50 W mA mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. *Typicals used for testing purposes. 7. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to −0.965 V. 8. All loading with 50 W to VCC − 2.0 V. VOH/VOL measured at VIH/VIL. 9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 10. VTHR is the voltage applied to the complementary input, typically VBB or VMM. VTHR(MIN) = VIHCMR + 75 mV. VTHR(MAX) = VIHCMR − 75 mV. 11. VIH cannot exceed VCC. 12. VIL always w VEE. http://onsemi.com 5 NBSG16VS Table 6. DC CHARACTERISTICS, INPUT WITH VARIABLE PECL OUTPUT VCC = 3.3 V; VEE = 0 V (Note 18) −40°C Symbol IEE VOH VOL Characteristic Negative Power Supply Current Output HIGH Voltage (Note 13) Output LOW Voltage (Note 13) (Max Swing) (VCTRL = VCC − 600 mV) Input HIGH Voltage (Single−Ended) (Notes 15 and 16) Input LOW Voltage (Single−Ended) (Notes 15 and 17) PECL Output Voltage Reference Input HIGH Voltage Common Mode Range (Note 1