2.5V/3.3V SiGe Differential 1:10 Clock/Data Driver

NBSG111 2.5V/3.3V SiGe Differential 1:10 Clock/Data Driver with RSECL* Outputs *Reduced Swing ECL Description http://onsemi.com MARKING DIAGRAM* The NBSG111 is a 1−to−10 differential clock/data driver. The device is functionally equivalent to the LVEP111 device with much higher bandwidth and lower EMI capabilities. Inputs incorporate internal 50 W termination resistors (input to VT pad) and accept NECL (Negative ECL), PECL (Positive ECL), LVTTL, LVCMOS, CML, or LVDS. Outputs are RSECL (Reduced Swing ECL), 400 mV. The Q[0:9] / Q[0:9] outputs have a differential synchronous enable (EN/EN) pin. The synchronous enable pin is used to avoid a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of selected clock (CLK0/CLK0 or CLK1/CLK1), therefore all associated specification limits are referenced to the negative edge of the selected clock input. The VBB and VMM pins are internally generated voltage supplies available to this device only. The VBB is used for single−ended NECL www.DataSheet4U.com or PECL inputs and the VMM pin is used for LVCMOS inputs. For single−ended input operation, the unused differential input is connected to VBB or VMM as a switching reference voltage. VBB or VMM may also rebias AC coupled inputs. When used, decouple VBB and VMM via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB and VMM outputs should be left open. Features SG 111 LYW FCBGA−49 BA SUFFIX CASE 489A SG111 L Y W = Device Code = Wafer Lot = Year = Work Week *For further details, refer to Application Note AND8002/D ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. • • • • • • • • • • Maximum Input Clock Frequency > 6 GHz Typical Maximum Input Data Rate > 6 Gb/s Typical 300 ps Typical Propagation Delay 60 ps Typical Rise and Fall Times RSPECL Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V RSNECL Output with RSNECL or NECL Inputs with Operating Range: VCC = 0 V with VEE = −2.375 V to −3.465 V RSECL Output Level (400 mV Peak−to−Peak Output), Differential Output 50 W Internal Input Termination Resistors Compatible with Existing 2.5 V/3.3 V LVEP and EP Devices VBB and VMM Reference Voltage Output © Semiconductor Components Industries, LLC, 2007 January, 2007 − Rev. 8 1 Publication Order Number: NBSG111/D NBSG111 1 2 3 4 5 6 7 A VEE Q9 Q9 Q8 Q8 Q7 VEE B Q0 VMM CLK1 CLK1 VCC NC Q7 C Q0 VEE VTCLK1 VTCLK1 VTSEL SEL Q6 D Q1 EN VTEN VCC VTSEL SEL Q6 E Q1 EN VTEN VTCLK0 VTCLK0 VEE Q5 F Q2 NC VCC CLK0 CLK0 VBB Q5 G VEE Q2 Q3 Q3 Q4 Q4 VEE Figure 1. BGA−49 Pinout (Top View) http://onsemi.com 2 NBSG111 Table 1. PIN DESCRIPTION Pin A1,A7,G1,G7,C2,E6 F3,D4,B5 B2 F6 E4 F4 E5 F5 C4 B4 C3 B3 B1,D1,F1,G3,G5,F7, D7,B7,A5,A3 C1,E1,G2,G4,G6,E7, C7,A6,A4,A2 D5 D6 C5 C6 D3 D2 E3 E2 F2,B6 Name VEE VCC VMM VBB VTCLK0 CLK0 VTCLK0 CLK0 VTCLK1 CLK1 VTCLK1 CLK1 Q[0:9] Q[0:9] VTSEL SEL VTSEL SEL VTEN EN VTEN EN NC I/O − − − − − ECL, CML, LVCMOS, LVDS, LVTTL Input − ECL, CML, LVCMOS, LVDS, LVTTL Input − ECL, CML, LVCMOS, LVDS, LVTTL Input − ECL, CML, LVCMOS, LVDS, LVTTL Input RSECL Output RSECL Output − ECL, CML, LVCMOS, LVDS, LVTTL Input − ECL, CML, LVCMOS, LVDS, LVTTL Input − ECL, CML, LVCMOS, LVDS, LVTTL Input − ECL, CML, LVCMOS, LVDS, LVTTL Input − Description Negative Supply Voltage. All VEE Pins Must be Externally Connected to Power Supply to Guarantee Proper Operation. Positive Supply Voltage. All VCC Pins Must be Externally Connected to Power Supply to Guarantee Proper Operation. LVCMOS Reference Voltage Output (VCC − VEE) / 2. ECL Reference Voltage Output Internal 50 W Termination Pin for CLK0. See Table 4. (Note 1) Noninverted Differential Input CLK0. Internal 75 kW to VEE. Internal 50 W Termination Pin for CLK0. See Table 4. (Note 1) Inverted Differential Input CLK0. Internal 75 kW to VEE and 36.5 kW to VCC. Internal 50 W Termination Pin 1. See Table 4. (Note 1) Noninverted Differential Input CLK1. Internal 75 kW to VEE. Internal 50 W Termination Pin for CLK1. See Table 4. (Note 1) Inverted Differential Input CLK1. Internal 75 kW to VEE and 36.5 kW to VCC. Noninverted Differential Outputs [0:9]. Typically Terminated with 50 W to VTT = VCC − 1.5 V Inverted Differential Outputs [0:9]. Typically Terminated with 50 W to VTT = VCC − 1.5 V Internal 50 W Termination Pin for SEL. See Table 4. (Note 1) Noninverted Differential Select Logic Input. Internal 75 kW to VEE. Internal 50 W Termination Pin for SEL. See Table 4. (Note 1) Inverted Differential Select Logic Input. Internal 75 kW to VEE and 36.5 kW to VCC. Internal 50 W Termination Pin for EN. See Table 4. (Note 1) Noninverted Differential Output Enable Pin. Internal 75 kW to VEE. Internal 50 W termination Pin for EN. See Table 4. (Note 1) Inverted Differential Output Enable Pin. Internal 75 kW to VEE and 36.5 kW to VCC. No Connect. The NC Pins are Electrically Connected to the Die and ”MUST BE” Left Open. 1. In the differential configuration when the input termination pins (VTCLK, VTDCLK) are connected to a common termination voltage and if no signal is applied, then the device will be susceptible to self−oscillation. http://onsemi.com 3 NBSG111 Table 2. FUNCTION TABLE SEL L L H H EN L H L H Active Input Disabled Outputs CLK0, CLK0 Disabled Outputs CLK1, CLK1 2. SEL/EN are the inverse of SEL/EN unless specified otherwise. Q0 (B1) Q0 (C1) Q1 (D1) Q1 (E1) (C5) VTSEL (C6) SEL RTIN R2 R1 Q2 (F1) Q2 (G2) Q3 (G3) (E4) VTCLK0 (F4) CLK0 (F5) CLK0 (E5) VTCLK0 (B4) CLK1 (C4) VTCLK1 (B3) CLK1 (C3) VTCLK1 (D6) SEL (D5) VTSEL RTIN R2 RTIN RTIN R2 RTIN R1 R2 1 (E2) EN (E3) VTEN 0 (D3) VTEN (D2) EN R2 SYNC R1 RTIN R2 (F6) VBB (A1, A7, G1, G7) VEE RTIN Q3 (G4) Q4 (G5) Q4 (G6) Q5 (F7) Q5 (E7) Q6 (D7) Q6 (C7) Q7 (B7) Q7 (A6) Q8 (A5) Q8 (A4) (B5, D4, F3) VCC (B2) VMM Q9 (A3) Q9 (A2) R1 R2 RTIN R2 Figure 2. Logic Diagram Table 3. INTERFACING OPTIONS INTERFACING OPTIONS CML LVDS AC−COUPLED CONNECTIONS Connect VTCLK0, VTCLK1, VTEN, VTSEL and VTCLK0, VTCLK1, VTEN, VTSEL to VCC Connect VTCLK0, VTCLK1, VTEN, VTSEL and VTCLK0, VTCLK1, VTEN, VTSEL Together Bias VTCLK0, VTCLK1, VTEN, VTSEL and VTCLK0, VTCLK1, VTEN, VTSEL Inputs within Common Mode Range (VIHCMR) Standard ECL Termination Techniques See Text on Page 1. Unused Differential Input Switching Voltage Reference Range is from VEE + 1125 mV to VCC − 75 mV RSECL, PECL, NECL LVTTL, LVCMOS http://onsemi.com 4 NBSG111 Table 4. ATTRIBUTES Characteristics Internal Input Pulldown Resistor, R2 (CLK0, CLK0, CLK1, CLK1, SEL, SEL, EN, EN) Internal Input Pullup Resistor, R1 (CLK0, CLK1, SEL, EN) ESD Protection Human Body Model Machine Model Charged Device Model Value 75 kW 36.5 kW > 2 kV > 100 V > 1 kV Level 3 Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in 479 Moisture Sensitivity (Note 3) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. Table 5. MAXIMUM RATINGS Symbol VCC VI VEE VINPP IOUT IIN IBB IMM TA Tstg qJA qJC Tsol Parameter Positive Power Supply Positive Input Negative Input Negative Power Supply Differential Input Voltage |CLK − CLK| Output Current Input Current Through RT (50 W Resistor) VBB Sink/Source VMM Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction−to−Ambient) (Note 4) Thermal Resistance (Junction−to−Case) Wave Solder 0 LFPM 500 LFPM 2S2P (Note 4) < 15 sec. 49 FCBGA 49 FCBGA 49 FCBGA Condition 1 VEE = 0 V VEE = 0 V VCC = 0 V VCC = 0 V VCC − VEE w 2.8 V VCC − VEE t 2.8 V Continuous Surge Static Surge VI  VCC VI  VEE Condition 2 Rating 3.6 3.6 −3.6 −3.6 2.8 |VCC − VEE| 25 50 45 80 1 1 −40 to +70 −65 to +150 67 57 2 to 4 225 Units V V V V V V mA mA mA mA mA mA °C °C °C/W °C/W °C/W °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. JEDEC standard 51−6, multilayer board − 2S2P (2 signal, 2 power). http://onsemi.com 5 NBSG111 Table 6. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT VCC = 2.5 V; VEE = 0 V (Note 5) −40°C Symbol IEE VOH VOUTPP VIH VIL VBB VIHCMR VMM RTIN IIH IIL Characteristic Negative Power Supply Current Output HIGH Voltage (Note 6) Output Voltage Amplitude Input HIGH Voltage (Single−Ended) (Notes 8 and 9) Input LOW Voltage (Single−Ended) (Notes 8 and 10) PECL Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 7) LVCMOS Output Voltage Reference (@ 2.5 VCC) Internal Input Termination Resistor Input HIGH Current (@ VIH) Input LOW Current (@ VIL) Min 70 1365 305 VTHR + 75 VIH − 2500 1025 1.2 Typ 85 1520 420 VCC − 1000* VCC − 1400* 1100 Max 110 1615 545 VCC VTHR − 75 1265 2.5 Min 70 1410 305 VTHR + 75 VIH − 2500 1025 1.2 25°C Typ 85 1530 420 VCC − 1000* VCC − 1400* 1100 Max 110 1660 545 VCC VTHR − 75 1265 2.5 Min 70 1435 305 VTHR + 75 VIH − 2500 1025 1.2 70°C Typ 85 1560 420 VCC − 1000* VCC − 1400* 1100 Max 110 1685 545 VCC VTHR − 75 1265 2.5 Unit mA mV mV mV mV mV V mV W mA mA 1050 45 1250 50 30 25 1450 55 100 100 1050 45 1250 50 30 25 1450 55 100 100 1050 45 1250 50 30 25 1450 55 100 100 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device s