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87C196KR KQ 87C196JV JT 87C196JR JQ ADVANCED 16-BIT CHMOS MICROCONTROLLER
Automotive
Y Y Y Y
b 40 C to a 125 C Ambient
Y
High Performance CHMOS 16-Bit CPU Up to 48 Kbytes of On-Chip EPROM Up to 1 5 Kbytes of On-Chip Register RAM Up to 512 Bytes of Additional RAM (Code RAM) Register-Register Architecture Up to 8 Channel 10-Bit A D with Sample Hold Up to 37 Prioritized Interrupt Sources Up to Seven 8-Bit (56) I O Ports Full Duplex Serial I O Port Dedicated Baud Rate Generator Interprocessor Communication Slave Port
Device Pins Package 68-pin PLCC 68-pin PLCC 52-pin PLCC 52-pin PLCC 52-pin PLCC 52-pin PLCC EPROM 16K 12K 48K 32K 16K 12K Reg RAM 488 360 1 5K 1 0K 488 360
Y Y Y
High Speed Peripheral Transaction Server (PTS) Two 16-Bit Software Timers 10 High Speed Capture Compare (EPA) Full Duplex Synchronous Serial I O Port (SSIO) Two Flexible 16-Bit Timer Counters Quadrature Counting Inputs Flexible 8- 16-Bit External Bus Programmable Bus (HLD HLDA) 1 75 ms 16 x 16 Multiply 3 ms 32 16 Divide 68-Pin and 52-Pin PLCC Packages
Y
Y Y Y Y Y Y Y
Y Y
Y Y Y Y Y
Code RAM 256 128 512 512 256 128
I O 56 56 41 41 41 41
EPA 10 10 6 6 6 6
SIO Y Y Y Y Y Y
SSIO Y Y Y Y Y Y
A D 8 8 6 6 6 6
87C196KR 87C196KQ 87C196JV 87C196JT 87C196JR 87C196JQ
The 87C196KR KQ JV JT JR JQ devices represent the fourth generation of MCS 96 Microcontroller products implemented on Intel’s advanced 1 micron process technology These products are based on the 80C196KB device with improvements for automotive applications The instruction set is a true super set of 80C196KB The 87C196JR is a 52-pin version of the 87C196KR device while the 87C196KQ JQ are memory scalars of the 87C196KR JR The 87C196JV JT A-step devices (JV-A JT-A) are the newest members of the MCS 96 microcontroller family These devices are memory scalars of the 87C196JR D-step (JR-D) and are designed for strict functional and electrical compatibility The JT-A has 32 Kbytes of on-chip EPROM 1 0 Kbytes of Register RAM and 512 bytes of Code RAM The JV-A has 48 Kbytes of on-chip EPROM 1 5 Kbytes of Register RAM and 512 bytes of Code RAM
Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT
INTEL CORPORATION 1995
November 1995
Order Number 270827-006
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87C196KR KQ 87C196JV JT 87C196JR JQ
The MCS 96 microcontroller family members are all high performance microcontrollers with a 16-bit CPU The 87C196Kx Jx family members listed above are composed of the high-speed (16 MHz) core as well as the following peripherals up to 48 Kbytes of Programmable EPROM up to 1 5 Kbytes of Register RAM 512 bytes of code RAM (16-bit addressing modes) with the ability to execute from this RAM space an eight channel-10-Bit g 3 LSB analog to digital converter with programmable S H times with conversion times k 5 ms at 16 MHz an asynchronous synchronous serial I O port (8096 compatible) with a dedicated 16-bit baud rate generator an additional synchronous serial I O port (8096 compatible) with a dedicated 16-bit baud rate generator an additional synchronous serial I O port with full duplex master slave transceivers a flexible timer counter structure with prescaler cascading and quadrature capabilities 10 modularized multiplexed high speed I O for capture and compare (called Event Processor Array) with 250 ns resolution and double buffered inputs a sophisticated prioritized interrupt structure with programmable Peripheral Transaction Server (PTS) The PTS has several channel modes including single burst block transfers from any memory location to any memory location a PWM and PWM toggle mode to be used in conjunction with the EPA and an A D scan mode Additional SFR space is allocated for the EPA and can be ‘‘windowed’’ into the lower Register RAM area Please refer to the following datasheets for higher frequency versions of devices contained within this datasheet 20 MHz 87C196JT Order 272529 20 MHz 87C196JV Order Number 272580
Up to 37 Interrupt Vectors Up to 512 Bytes of Code RAM Up to 1 5 Kbytes of Register RAM
‘‘Windowing’’ Allows 8-Bit Addressing to Some 16-Bit Addresses 1 75 ms 16 x 16 Multiply 3 ms 32 16 Divide
Oscillator Fail Detect
PERIPHERAL FEATURES
Programmable A D Conversion and S H Times 10 Capture Compare I O with 2 Flexible Timers Synchronous Serial I O Port for Full Duplex Serial I O
Total Utilization of ALL Available Pins (I O Mux’d
with Control)
2 16-Bit Timers with Prescale Cascading and
Quadrature Counting Capabilities
Up to 12 Externally Triggered Interrupts
NEW INSTRUCTIONS XCH XCHB
Exchange the contents of two locations either Word or Byte is supported
BMOVi
Interruptable Block Move Instruction allows the user to be interrupted during long executing Block Moves
ARCHITECTURE
The 87C196KR KQ JV JT JR JQ are members of the MCS 96 microcontroller family has the same architecture and uses the same instruction set as the 80C196KB KC Many new features have been added including
TIJMP
Table Indirect JUMP This instruction incorporates a way to do complex CASE level branches through one instruction An example of such code savings several interrupt sources and only one interrupt vector The TIJMP instruction will sort through the sources and branch to the appropriate sub-code level in one instruction This instruction was added especially for the EPA structure but has other code saving advantages
CPU FEATURES
Powerdown and Idle Modes 16 MHz Operating Frequency A High Performance Peripheral Transaction Server (PTS)
EPTS DPTS
Enable and Disable PTS Interrupts (Works like EI and DI)
2
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87C196KR KQ 87C196JV JT 87C196JR JQ
SFR OPERATION
An additional 256 bytes of SFR registers were added to the 8XC196KR devices These locations were added to support the wide range of on-chip peripherals that the 8XC196KR has This memory space (1F00 – 1FFFH) has the ability to be addressed as direct 8-bit addresses through the ‘‘windowing’’ technique Any 32- 64- or 128-byte section can be relocated in the upper 32 64 or 128 bytes of the internal register RAM (080 – FFH) address space
270827 – 1
Figure 1 Block Diagram
270827 – 15
Figure 2 The 8XC196KR Family Nomenclature
3
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87C196KR KQ 87C196JV JT 87C196JR JQ
270827 – 2
270827 – 3
Figure 3 Package Diagrams
4
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87C196KR KQ 87C196JV JT 87C196JR JQ
PIN DESCRIPTIONS
Symbol VCC VSS VSS VSS VREF Main supply voltage ( a 5V) Digital circuit ground (0V) There are three VSS pins all of which MUST be connected to a single ground plane Reference for the A D converter ( a 5V) VREF is also the supply voltage to the analog portion of the A D converter and the logic used to read Port 0 Must be connected for A D and Port 0 to function Programming voltage for the EPROM parts It should be a 12 5V for programming It is also the timing pin for the return from powerdown circuit Connect this pin with a 1 mF capacitor to VSS and a 1 MX resistor to VCC If this function is not used VPP may be tied to VCC Reference ground for the A D converter Must be held at nominally the same potential as VSS Input of the oscillator inverter and the internal clock generator Output of the oscillator inverter Output of the internal clock generator The frequency is frequency It has a 50% duty cycle Also LSIO pin the oscillator Name and Function
VPP
ANGND XTAL1 XTAL2 P2 7 CLKOUT RESET
Reset input to the chip Input low for at least 16 state times will reset the chip The subsequent low to high transition resynchronizes CLKOUT and commences a 10state time sequence in which the PSW is cleared bytes are read from 2018H and 201AH loading the CCBs and a jump to location 2080H is executed Input high for normal operation RESET has an internal pullup Input for bus width selection If CCR bit 1 is a one and CCR1 bit 2 is a one this pin dynamically controls the Bus width of the bus cycle in progress If BUSWIDTH is low an 8-bit cycle occurs If BUSWIDTH is high a 16-bit cycle occurs If CCR bit 1 is ‘‘0’’ and CCR1 bit 2 is ‘‘1’’ all bus cycles are 8-bit if CCR bit 1 is ‘‘1’’ and CCR1 bit 2 is ‘‘0’’ all bus cycles are 16-bit CCR bit 1 e ‘‘0’’ and CCR1 bit 2 e ‘‘0’’ is illegal Also an LSIO pin when not used as BUSWIDTH A positive transition causes a non-maskable interrupt vector through memory location 203EH Used by Intel (GND this pin) Output high during an external memory read indicates the read is an instruction fetch INST is valid throughout the bus cycle INST is active only during external memory fetches during internal EP ROM fetches INST is held low Also LSIO when not INST Input for memory select (External Access) EA equal to a high causes memory accesses to locations 2000H through 5FFFH to be directed to on-chip EPROM ROM EA equal to a low causes accesses to these locations to be directed to offchip memory EA e a 12 5V causes execution to begin in the Programming Mode EA latched at reset Address Latch Enable or Address Valid output as selected by CCR Both pin options provide a latch to demultiplex the address from the address data bus When the pin is ADV it goes inactive (high) at the end of the bus cycle ADV can be used as a chip select for external memory ALE ADV is active only during external memory accesses Also LSIO when not used as ALE
P5 7 BUSWIDTH
NMI P5 1 INST
EA
P5 0 ALE ADV
5
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87C196KR KQ 87C196JV JT 87C196JR JQ
PIN DESCRIPTIONS (Continued)
Symbol P5 3 RD P5 2 WR WRL Name
