XRC 100 BASE-TX/FX REPEATER CONTROLLER

INDEX www.DataSheet4U.com MX98741 XRC 100 BASE-TX/FX REPEATER CONTROLLER 1.0 FEATURES • Eight 100 BASE-TX/FX ports; each port individually configurable to TX or FX • Direct interface with analog clock generation/recovery chips • Three Media Independent Interface (MII) • Expandable to increase number of repeater ports • Low latency design simplified high port number Class II repeater implementation • Management features accessible through MII or serial ports • All ports can be separately isolated or partitioned in reponse to fault conditions • Conforms to IEEE 802.3u Repeater Unit Specification • LED display for TX/FX port activities and collisions • 208-pin, CMOS device in PQFP package 2.0 GENERAL DESCRIPTION The MX98741 (100BASE-TX Repeater Controller, XRC) is a 208-pin PQFP device that interfaces directly with offshell clock generation/recovery chips. Eight ports can be configured as 100 BASE-TX or FX ports individually. Three additional ports have Media Independent Interfaces (MII) which allow easy connection of management and bridge devices. The expansion port allows multiple XRCs to be linked together to form a repeater of high port counts. LEDs are provided for visual monitoring of TX/FX port activities and collisions. The XRC's design inserts minimum delay between the TX/FX ports and the expansion port. A master-slave type arbitration is also implemented to shorten the communciation time among multiple XRCs. As a result, design for Class II stackable hub is greatly simplified. Control Functions and management status are implemented through internal registers. These registers are accessed via either standard MII management interface (MDC, MDIO) or several serial ports. These serial ports are accessed easily by hardware for debugging and configuration purposes. A dedicated management chip can also utilize these serial ports to access the XRC. P/N:PM0342 REV. 1.4, NOV. 07, 1998 1 INDEX www.DataSheet4U.com MX98741 3.0 PIN CONFIGURATION VCC RSCLK3 SIGDET3 RDAT30 RDAT31 RDAT32 RDAT33 RDAT34 GND GND TDAT30 TDAT31 TDAT32 TDAT33 TDAT34 GND GND RSCLK4 SIGDET4 VCC RDAT40 RDAT41 RDAT42 RDAT43 RDAT44 GND TDAT40 TDAT41 TDAT42 TDAT43 TDAT44 RSCLK5 SIGDET5 RDAT50 RDAT51 RDAT52 RDAT53 RDAT54 VCC VCC TDAT50 TDAT51 TDAT52 TDAT53 TDAT54 GND SCRCTRL RESETL XCOLED TEST TSEL GND 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 GND GND MDC MDIO CRSC RXDVC TXERC TXDC3 TXDC2 TXDC1 TXDC0 TXENC VCC RXCLKJ COL RXER RXD3 RXD2 RXD1 RXD0 GND TXCLK COCLK VCC CRSE RXDVB TXERB TXDB3 TXDB2 TXDB1 TXDB0 TXENB GND CRSA RXDVA TXERA TXDA3 TXDA2 TXDA1 TXDA0 TXENA TDAT24 TDAT23 TDAT22 TDAT21 TDAT20 RDAT24 RDAT23 RDAT22 RDAT21 RDAT20 GND MX98741 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 GND SIGDET2 RSCLK2 GND TDAT14 TDAT13 TDAT12 TDAT11 TDAT10 VCC RDAT14 RDAT13 RDAT12 RDAT11 RDAT10 VCC SIGDET1 RSCLK1 ACTP7 ACTP6 ACTP5 ACTP4/XRCADD4 VCC ACTP3/XRCADD3 ACTP2/XRCADD2 ACTP1/XRCADD1 ACTP0/XRCADD0 GND ANYACT BDATENL EXTCRS JAMI JAMO GND EFAT4 EDAT3 EDAT2 EDAT1 EDAT0 VCC VCC TDAT04 TDAT03 TDAT02 TDAT01 TDAT00 RDAT04 RDAT03 RDAT02 RDAT01 RDAT00 GND P/N:PM0342 GND RSCLK6 SIGDET6 RDAT60 RDAT61 RDAT62 RDAT63 RDAT64 TDAT60 TDAT61 TDAT62 TDAT63 TDAT64 GND RSCLK7 SIGDET7 RDAT70 RDAT71 RDAT72 RDAT73 RDAT74 GND TDAT70 TDAT71 TDAT72 TDAT73 TDAT74 VDD VCC XACTLED0 XACTLED1 XACTLED2 XACTLED3 XACTLED4 XACTLED5 XACTLED6 XACTLED7 GND VCC REGCK REGLTCH GND RDXWR PIDISI PTSCEN JBFLO PARTNK ISC GND RSCLKO SIGDETO GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 REV. 1.4, NOV. 07, 1996 2 INDEX www.DataSheet4U.com MX98741 4.0 PIN DESCRIPTION Table 4-1 Pin Description for MX98741 A. MX Data Transceiver (Am78965/Am78966 or MC68836), 98 pins Name I/O Description TDAT[0:7][0:4] O, EXP Transmit Data. These five outputs are 4B/5B encoded transmit data symbols, driven at the rising edge of TXCLK. TDAT4 is the Most Significant Bit. PAD # 59-63 96-100 111-115 167-171 183-187 197-201 9-13 23-27 135 TXCLK I, TTL 54-58 90-94 106-110 160-164 177-181 190-194 4-8 17-21 50,87 102,158 174,188 2,15 51,88 103,159 175,189 3,16 134 RDAT[0:7][0:4] I, TTL Transmit Clock. This pin supplies the frequency reference to the transmit logic. It should be driven by an external 25 MHz crystal-controlled clock source. Receive Data. These 5-bit parallel data symbols from transceiver are latched by the rising edge of RSCLK. RDAT4 is the Most Significant Bit. RSCLK[0:7] I, TTL Recovered Sumbol Clock. This is a 25 MHz clock, which is derived from the clock synchroniztion PLL circuit. SIGDET[0:7] I, TTL Signal Detect. This signal indicates that the received signal is above the detection threshold and will be used for the link test state machine. Core Clock. 50M Clock input used by Repeater Core. COCLK I, TTL P/N:PM0342 REV. 1.4, NOV. 07, 1996 3 INDEX www.DataSheet4U.com MX98741 B. Expansion Port, 18 pins I/O Description O, TTL Forced Jam Out. Active High. The OR’d forced jam signals exclude JAMI input) controlled by Carrier Integrity Monitor of each port. If collision occurs inside the XRC, this pin is also asserted. I, Schm Forced Jam Input. Active High. Asserted by external arbiter, and XRC will generate JAM patterns to all its ports. Note : Glitch on JAMI and EDATENL may cause internal state machine malfunction. I, Schm Enable Expansion Data. Active Low. Asserted by an external arbitor. XRC will drive data into EDAT. I/O, EXP Expansion Data. Bidirectional 5-bit wide data. By default, EDAT is an input. When EDATENL is low, EDAT changed from input mode to output mode. Internally pull-up. O, TTL Activity Out. This is the activity of port 5..8 synchronous to COCLK (50M clock used by core). It also serves as data framing signal for the packet on EDAT. ACTP leads EDAT's /J/K/ pattern by more than 80 ns and deasserted 40ns after the /T/R/ or the last byte of jam patterns. I/O, TTL Activity Out/Physical Address. When RESETL goes high, value on ACTP[0;4] will be latched into internal buffer as physical address of XRC. After reset, these five pins have the same function as ACTP[5:8]. O, TTL Any Activity. Active High. The OR’d ACTP[7:0] and TXEN A to C. This is used as an indication that an XRC is ready to drive data into EDAT. I, Schm External Carrier Sense. Active high. Asserted by an external arbitor indicating activity from other XRC's at the expansion port. C. Miscellaneous Pins, 2 pins I, Schm Reset. Active Low. This signal is output by the system to reset all the logic on the chip. I, TTL Scrambler Control. If high, the scrambler/descrambler of each port is individually controlled by MII register 17. If low, the scrambler/ descrambler is bypassed in all the ports. PAD # 72 Name JAMO 73 JAMI 75 66-70 EDATENL EDAT[0:4] 84-86 ACTP[5:8] 78-81, 83 ACTP[0:4] /XRCADD[0:4] 76 ANYACT 74 EXTCRS 204 203 RESETL SCRCTRL P/N:PM0342 REV. 1.4, NOV. 07, 1996 4 INDEX www.DataSheet4U.com MX98741 D. Register Access Pins, 8 pins Description Partition/Link Status. This pin shows the status of internal register #18 in round-robin fashion starting at port 0 partition status and ending at port7 Link Status after REGLTCH is deasserted. Jabber/Buffer Status. This pin shows the status of internal register #19 in round-robin fashion starting at port 0 Jabber Status and ending at port 7 Elastic Buffer Over/Underflow Status after REGLTCH is deasserted. Port/Scrambler Enable. If RDXWR is high, each port's enable/disable status (register #17) will be displayed at the rising edge of REGCK in round-robin fashion starting at port 0 Port 0 Enable status and ending at port 7 Scrambler Enable status after REGLTCH is deasserted. If RDXWR is low, 16-bit data can be written into the XRC at the rising edge of REGCK in round-robin fashion starting at port 0 Port Enable Signal and ending at port 7 Scrambler enable after REGLTCH is asserted high. Internally pull-up. Partition/Isolation Disable. If RDXWR is high, each port's partition/ Isolation Disable status will be displayed at the rising edge of REGCK in round-robin fashion starting at port 0 partition disable status and ending at port7 Isolation Disable status after REGLTCH is deasserted. If RDXWR is low, 16-bit data can be written into the XRC at the rising edge of REGCK in round-robin fashion starting at port 0 partition disable status and ending at port 7 Isolation disable status after REGLTCH is asserted high. Internally pull-down. Isolation. Active High. Each port's isolation status will be displayed at the rising edge of REGCK in round-robin fashion starting at port0 after REGLTCH is deasserted. Read/Write. High indicates "Read" mode; register is being read out. REGLTCH is output. Low indicates "Write" mode; control registers are being written and REGLTCH is input. When RDXWR is programmed to "Write" Mode, internal "Read" status machine will be reset immediately. Register Latch. An output if RDXWR is high; an input if RDXWR is low. At the rising edge of REGCK, PARTLNK, JBFLO, PTSCEN, PIDIS, ISO display bit 0 status of corresponding registers, at the rising edge of next REGCK, bit 1 status is displayed, etc. After bit 15 is displayed, REGLTCH is asserted at the rising edge of next REGCK. Note : Both Data and REGLTCH are driven at the falling edge of REGCK inside the XRC. To make sure the data setup time, it is strongly recommended that the frequency of REGCK is below 12.5 MHz. Internally pull-down. Register Clock. A clock used as refere