SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER

www.DataSheet4U.com ADVANCED INFORMATION MX98726 SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER WITH uP INTERFACE 1.0 Features • Direct interface to 80188/186 up to 40Mhz. • Integrated 10/100 TP tranceiver on chip to reduce overall cost • Fully comply to IEEE 802.3u spec. • Best fit in network printer and hub/switch management application • A local DMA channel between on-chip FIFOs and packet memory • Shared memory architecture allow host and MX98726 to use only one single SRAM • Host DMA can share packet memory with local DMA with simple hand shake protocol for x188/186 type of processor • Support bus size configuration: - CPU : 8 bits, SRAM: 8 bits - CPU : 16 bits, SRAM: 8/16 bits • Flexible packet buffer partition and addressing space for 32k, 64k up to 512 bytes • NWAY autonegociation function to automatically set up network speed and protocol • 3 loop back modes for system level diagnostics • Rich on-chip register set to support a wide variety of network management functions • Support 64 bits hash table for multicast addressing • Support software EEPROM interface for easy upgrade of EEPROM content • Support 1K bits and 4K bits EEPROM interface • 5V CMOS in 128 PQFP package for minimum board size application 1.1 Introduction MX98726 ( Generic MAC , or GMAC ) is a cost effective solution as a generic single chip 10/100 Fast Ethernet controller. It is designed to directly interface 80188, 80186 ( host ) without glue logic. Two types of memory sharing schemes are supported, i.e. interleaved and shared mode to support a variety of applications. Single chip solution will help reduce system cost not only on the components but also the board size. Full NWAY function with 10/100 tranceiver will ease the field installation, simply plug the chip in and it will connect itself with the best protocol available. The interleaved mode allow uP to access SRAM ( packet/host buffer ) through MX98726's local DMA channel. This way, no extra SRAM interface logic is needed on the host side. If high performance is desired, then shared memory mode is another alternative which allow host to access SRAM on its own by denying SRAM bus grant to MX98726 using simple hand shake protocol. Without SRAM bus grant, MX98726 will float its interface connected to the SRAM, therefore host can utilize its own memory subsystem to conduct its own SRAM access. A intelligent built-in SRAM bus arbitor will manage all the SRAM access requests from host, on-chip transmit channel and on-chip receive channel. The throughput of these network channels and MX98726's DMA burst length can be easily adjusted by option bits on the chip. These options can help system developers to "fine tune" a best cost/performance ratio. MX98726 is also equipped with fast back-to-back transmit capability which allow software to "fire" as many transmit packets as needed in a single command. Receive FIFO also allow back-to-back reception. Optional EEPROM can be used to stored network network address and other information. In case cost is really a concern, most configuration options including network address can be programmed through uP. P/N:PM0555 MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice. REV. 0.9.8, FEB. 14, 2000 1 www.DataSheet4U.com MX98726 1.2 Internal Block Diagram Packet Buffer (SRAM) EPROM SRAMIU Serial ROM port Host BIU RX FIFO RX SM TX FIFO TX SM PCS NWAY CTRL & REGS 100 TX PHY 100TX PMD interface 10Mbps MCC+TP interface MX98726 Architecture and Interface overview P/N:PM0555 MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice. REV. 0.9.8, FEB. 14, 2000 2 www.DataSheet4U.com MX98726 1.3 Typical Applications Packet buffer EPROM C46/C66 local DMA uP with dedicate bus Host side CSB decode Customer Application MX98726 RJ45 Xformer TP cable Interleaved memory Architecture Host Memory Subsystem SRAM Bus Packet buffer EPROM C46/C66 HOLD RJ45 uP with shared bus HLDA Xformer MX98726 TP cable CSB Decode Customer Application Shared memory Architecture P/N:PM0555 MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice. REV. 0.9.8, FEB. 14, 2000 3 www.DataSheet4U.com MX98726 2.0 Pin Configuration and Description MWE1B MWE0B PSENB MOEB CLKIN MCSB BHEB SRDY RSTB LED0 LED1 AD10 67 AD11 66 WRB INTB GND GND 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 65 GND MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 VDD VDD RDB AD8 AD9 ALE A16 A17 A18 A19 MD10 MD11 GND MD12 MD13 MD14 MD15 EECS MA0(EECK) GND MA1(EEDI) MA2(EEDO) MA3 MA4 MA5 MA6 MA7 VDD MA8 MA9 MA10 MA11 MA12 MA13 MA14 GND 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 1 2 3 4 5 6 7 8 9 GND VDD AD12 AD13 AD14 AD15 VDD AD0 AD1 GND AD2 AD3 AD4 AD5 AD6 AD7 MIO CSB HLDA HOLD C46/C66 UPTYPE1 UPTYPE0 GNDA VDDA GNDA MX98726 CKREF(X1) GNDA GNDA VDDA GNDR VDDR RXIN RXIP VDDR GNDR GNDR VDDA TXOP GNDA CPK RXT2EQ VDDA GNDA GNDA TXON VDDA GNDA P/N:PM0555 MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice. VDDA REV. 0.9.8, FEB. 14, 2000 4 VDDA MA15 MA16 MA17 MA18 MA19 TXD3 TXD2 TXD1 TXD0 GND VDD RDA RTX X2 www.DataSheet4U.com MX98726 2.1 Pin Description : ( all internal pull-up resistor is 168K ohm, pull-down is 70k ohm ) PIN# 82 49-54, 56,57 59-62, 66-69 76 70-73 79 78 81 Pin Name CLKIN AD[7:0] AD[15:8] ALE A[19:16] RDB WRB INTB Type I, TTL I/O, 4ma I/O, 4ma I,TTL I, TTL I, TTL I, TTL O/D, 4ma Description Host Clock Input : 8M to 40 Mhz. Multiplexed Address/Data Bit [7:0] : Multiplexed Address/Data Bit [15:8] : Address Latch Enable : Active high Host Address Bit [19:16] : Internal pull-down Host Read Strobe: Active low. Host Write Strobe : Active low. Host Interrupt Output : Polarity can be programmed, default is active low. For active Low interrupt application, external pull-up is reguired. For active high interrupt application, external pull-down is required. Host Byte High Enable : BHEB A0 Function 0 0 Word Transfer 0 1 Upper Byte Transfer 1 0 Lower Byte Transfer 1 1 Lower Byte Transfer Synchronous Host Ready Output : Active high synchronized to CLKIN to indicate data is ready to be transferred. Initially low at the beginning of a host cycle. Chip Select : Active low, used to enable GMAC to decode host address. When high, no host cycle is recognized by MAC. Host Memory/IO cycle indicator : Set for memory access and reset for IO access. Internal pull-up. Decode of MIO can be disable by DISMIO register bit. Default is enabled. Packet Memory Bus Hold Request : Active high to request Host to "float" its interface of the packet memory. Host grants the packet buffer bus to MX98726 by asserting HLDA = 1. Packet Memory Bus Hold Acknowledge: Packet buffer bus is granted to MX98726. If HLDA=0 then MX98726 will float its interface on the packet buffer. Internal pull-up. Host Program Strobe Enable : Active low to indicate current cycle is a ROM access and MX98726 will not decode this ROM cycle. PSENB must high for packet memory access. Host Reset Input : Active low 75 BHEB I,TTL 80 SRDY O, 4ma 47 48 CSB MIO I, TTL I, TTL 45 HOLD O, 4ma 46 HLDA I, TTL 77 PSENB I, TTL 74 RSTB I,TTL P/N:PM0555 MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice. REV. 0.9.8, FEB. 14, 2000 5 www.DataSheet4U.com MX98726 Packet Buffer Interface : PIN# 4-7,1, 115-119 90-96, 98-104, 106-109 114 Pin Name MA[19:3] MD[15:0] Type O,4ma I/O,4ma Description Memory Address Bit 19-0: If HLDA = 0 then all these address lines are tristated. Memory Data Bit 15-0: MA2(EEDO) 1/O,4ma Memory Address Bit 2 or EEPROM Data Out bit: Right after host reset, GMAC automatically load configuration information from external EEPROM. During this period, MA2 pin acts as a EEDO pin that read in output data stream from EEPROM. After EEPROM auto load sequence is done, this pin becomes MA2 together with MA[19:3] forms packet buffer address line 19 - 0. Internally pull-down. Memory Address Bit 1 or EEPROM Data In bit: During EEPROM auto load sequence, MA1 pin acts as EEDI pin that write data stream into EEPROM. After EEPROM auto load sequence is done, this pin becomes MA1, together with MA[19:2] forms packet buffer address lines. Memory Address Bit 0 or EEPROM Clock Input : During EEPROM auto load sequence, MA0 pin acts as EECK pin that provides clock to EEPROM. After EEPROM auto load sequence is done, this pin becomes MA0, together with MA[19:1] forms packet buffer address lines. Memory Output Enable: Active low during packet buffer read access. Memory Chip Select: Active low during packet buffer accesses. Byte Write Enable: Active low during packet buffer write cycle. MWEB1 for high byte and MWEB0 for low byte. 113 MA1(EEDI) 1/O,4ma 111 MA0(EECK) 1/O,4ma 87 86 88, 89 MOEB MCSB MWEB[1:0] O,4ma O,4ma O,4ma P/N:PM0555 MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice. REV. 0.9.8, FEB. 14, 2000 6 www.DataSheet4U.com MX98726 10/100 Tranceiver interface : PIN# 14 17 16 23 24 29 30 32 33 34 Pin Name RDA CKREF(X1) X2 RXIN RXIP TXON TXOP CPK RTX2EQ RTX Type O I, TTL O I I O O O O O Description RDA external resistor to ground: 10K ohm, 5% 25Mhz , 30 PPM external osc./crystal input : 25Mhz , 30 PPM external crystal output : Twisted pair receive differential input: support both 10/100 Mbps speed Twisted pair receive differential input: support both 10/100 Mbps speed Twisted pair transmit differential