SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER

www.DataSheet4U.com MX98726EC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER WITH uP INTERFACE 1.0 Features • Direct interface to 80188/186 up to 40Mhz. • Integrated 10/100 TP tranceiver on chip to reduce overall cost • Optional MII interface for external tranceiver. • Fully comply to IEEE 802.3u spec. • Best fit in network printer and hub/switch management application • A local DMA channel between on-chip FIFOs and packet memory • Shared memory architecture allow host and MX98726EC to use only one single SRAM • Host DMA can share packet memory with local DMA with simple hand shake protocol for x188/186 type of processor • Supports proprietary local DMA channel to share packet memory • Support bus size configuration: - CPU : 8 bits, SRAM: 8 bits - CPU : 16 bits, SRAM: 8/16 bits • Flexible packet buffer partition and addressing space for 32k, 64k up to 512K bytes • NWAY autonegotiation function to automatically set up network speed and protocol • 3 loop back modes for system level diagnostics • Rich on-chip register set to support a wide variety of network management functions • Support 64 bits hash table for multicast addressing • Support software EEPROM interface for easy upgrade of EEPROM content • Support 1K bits and 4K bits EEPROM interface • 5V CMOS in 128 PQFP package for minimum board size application 1.1 Introduction MX98726EC ( Generic MAC , or GMAC ) is a cost effective solution as a generic single chip 10/100 Fast Ethernet controller. It is designed to directly interface 80188, 80186 ( host ) without glue logic. Two types of memory sharing schemes are supported, i.e. interleaved and shared mode to support a variety of applications. Single chip solution will help reduce system cost not only on the components but also the board size. Full NWAY function with 10/100 tranceiver will ease the field installation, simply plug the chip in and it will connect itself with the best protocol available. The interleaved mode allow uP to access SRAM ( packet/host buffer ) through MX98726EC's local DMA channel. This way, no extra SRAM interface logic is needed on the host side. If high performance is desired, then shared memory mode is another alternative which allow host to access SRAM on its own by denying SRAM bus grant to MX98726EC using simple hand shake protocol. Without SRAM bus grant, MX98726EC will float its interface connected to the SRAM, therefore host can utilize its own memory subsystem to conduct its own SRAM access. A intelligent built-in SRAM bus arbitor will manage all the SRAM access requests from host, on-chip transmit channel and on-chip receive channel. The throughput of these network channels and MX98726EC's DMA burst length can be easily adjusted by option bits on the chip. These options can help system developers to "fine tune" a best cost/performance ratio. MX98726EC is also equipped with fast back-to-back transmit capability which allow software to "fire" as many transmit packets as needed in a single command. Receive FIFO also allow back-to-back reception. Optional EEPROM can be used to stored network network address and other information. In case cost is really a concern, most configuration options including network address can be programmed through uP. P/N:PM0729 REV. 1.1, MAY. 28, 2001 1 www.DataSheet4U.com MX98726EC 1.2 Internal Block Diagram Packet Buffer (SRAM) EPROM SRAMIU Serial ROM port Host BIU RX FIFO RX SM TX FIFO TX SM MII Interface PCS NWAY CTRL & REGS 100 TX PHY 100TX PMD interface 10Mbps MCC+TP interface Architecture and Interface overview 1.3 Typical Applications Packet buffer EPROM C46/C66 local DMA uP with dedicate bus Host side CSB decode Customer Application MX98726EC RJ45 Xformer TP cable Interleaved memory Architecture P/N:PM0729 REV. 1.1, MAY. 28, 2001 2 www.DataSheet4U.com MX98726EC Host Memory Subsystem SRAM Bus Packet buffer EPROM C46/C66 HOLD uP with shared bus HLDA RJ45 Xformer MX98726EC TP cable CSB Decode Customer Application Shared memory Architecture 1.4 Combo Application Packet Host Memory Subsystem Local DMA buffer EPROM C46/C66 1M 8PHY or 10M 8PHY Customer Application Host CSB Decode MX98726EC RJ11 Phone Line Xformer TP Cable or RJ45 Xformer COMBO APPLICATION P/N:PM0729 REV. 1.1, MAY. 28, 2001 3 www.DataSheet4U.com P/N:PM0729 GND EECS VDD MA2(EEDO) MA1(EEDI) MD15 MD14 MD13 MD12 MD11 MD10 MA0(EECK) MA14 GND MA9 MA8 MA7 MA6 MA5 MA4 MA3 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 MA13 MA12 MA11 MA10 GND 128 MA15 1 102 MD9 MD8 MD7 MD6 MD5 VDD MD4 MD3 MD2 GND VDD MD1 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 MD0 MWE1B MWE0B MOEB MCSB GND LED0(TXC) LED1(TXEN) CLKIN INTB SRDY RDB WRB PSENB ALE BHEB RSTB A16(COL) A17(CRS) A18(RXDV) A19(RXC) AD8 AD9 AD10 AD11 GND 101 100 99 98 97 96 95 94 93 92 91 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 GND VDD (RXD3)MA16 (RXD2)MA17 (RXD1)MA18 (RXD0)MA19 TXD3 TXD2 TXD1 TXD0 VDDA GNDA RDA VDDA X2 CKREF(X1) GNDA GNDA VDDA GNDR VDDR RXIN RXIP VDDR GNDR GNDR VDDA TXON TXOP GNDA CPK RXT2EQ RTX VDDA GNDA GNDA VDDA 2.0 Pin Configuration and Description MX98726EC 4 MIO AD7 AD6 AD5 AD4 AD3 AD2 AD1 CSB GND HLDA VDDA HOLD GNDA GNDA C46/C66 UPTYPE1(MDC) UPTYPE0(MDIO) AD0 VDD VDD GND AD15 AD14 AD13 AD12 MX98726EC REV. 1.1, MAY. 28, 2001 www.DataSheet4U.com MX98726EC 2.1 Pin Description : PIN# 82 49-54, 59-62, 76 70 Pin Name CLKIN AD[7:0] AD[15:8] ALE A19(RXC) Type I, TTL I/O, 4ma 56,57 I/O, 4ma 66-69 I,TTL I, TTL Description Host Clock Input : 8M to 40 Mhz. Multiplexed Address/Data Bit [7:0] : Internal pull-down Multiplexed Address/Data Bit [15:8] : Internal pull-down Address Latch Enable : Active high Host Bus Address Bit19, when on-chip tranceiver is used,it is used in A[19:16], when in MII mode, it is defined as receive clock RXC (25MHz or 2.5MHz) When this pin is used as address bit, it is internally grounded until Reg50.6 (A19A16EN bit) is set to enable decoding of this pin as address bit. Internal pull-up Host Bus Address Bit18, when on-chip tranceiver is used,it is used in A[19:16], when in MII mode, it is defined as receive data valid RXDV signal. When this pin is used as address bit, it is internally grounded until Reg50.6 (A19A16EN bit) is set to enable decoding of this pin as address bit. Internal pull-up. Host Bus Address Bit17, when on-chip tranceiver is used, it is used in A[19:16], when in MII mode, it is defined as carrier same CRS signal. When this pin isused as address bit, it is internally grounded until Reg50.6 (A19A16EN bit) is set to enable decoding of this pin as address bit. Internal pull-up. Host Bus Address Bit16, when on-chip tranceiver is used, it is used in A[19:16], when in MII mode, it is defined as collision COL signal. When this pin is used as address bit, it is internally grounded until Reg50.6 (A19A16EN bit) is set to enable decoding of this pin as address bit. Internal pull-up. Host Read Strobe: Active low. Internal pull-up Host Write Strobe : Active low. Internal pull-up Host Interrupt Output : Polarity can be programmed, default is active low. For active Low interrupt application, external pull-up is reguired. For active high interrupt application, external pull-down is required. Host Byte High Enable : Internal pull-up. BHEB A0 Function 0 0 Word Transfer 0 1 Upper Byte Transfer 1 0 Lower Byte Transfer 1 1 Lower Byte Transfer Synchronous Host Ready Output : Active high synchronized to CLKIN to indicate data is ready to be transferred. Initially low at the beginning of a host cycle. Chip Select : Active low, used to enable GMAC to decode host address. When high, no host cycle is recognized by MAC. Host Memory/IO cycle indicator : Set for memory access and reset for IO access. Internal pull-up. Decode of MIO can be disable by DISMIO register bit. Default is enabled. REV. 1.1, MAY. 28, 2001 71 A18(RXDV) I,TTL 72 A17(CRS) I,TTL 73 A16(COL) I,TTL 79 78 81 RDB WRB INTB I, TTL I, TTL O/D, 4ma 75 BHEB I,TTL 80 SRDY O, 4ma 47 48 CSB MIO I, TTL I, TTL P/N:PM0729 5 www.DataSheet4U.com MX98726EC 45 HOLD O, 4ma Packet Memory Bus Hold Request : Active high to request Host to "float" its interface of the packet memory. Host grants the packet buffer bus to MX98726EC by asserting HLDA = 1. Packet Memory Bus Hold Acknowledge: Packet buffer bus is granted to MX98726EC. If HLDA=0 then MX98726EC will float its interface on the packet buffer. Internal pull-up. Host Program Strobe Enable : Active low to indicate current cycle is a ROM access and MX98726EC will not decode this ROM cycle. PSENB must high for packet memory access. Internal pull-up. Host Reset Input : Active low, Schmitt trigger input, Internal pull-up. 46 HLDA I, TTL 77 PSENB I, TTL 74 RSTB I,TTL Packet Buffer Interface : PIN# Pin Name Type O,4ma I/O, 4ma I/O, 4ma I/O, 4ma I/O, 4ma I/O,4ma Description Memory Address Bit 19-0: If HLDA = 0 then all these address lines are tristated. Memory Address Bit19, when on-chip tranceiver is used, it is defined as MA19, while in MII mode, it is used as receive data bit RXD0 pin. Memory Address Bit18, when on-chip tranceiver is used, it is defined as MA18, while in MII mode, it is used as receive data bit RXD1 pin. Memory Address Bit17, when on-chip tranceiver is used, it is defined as MA17, while in MII mode, it is used as receive data bit RXD2 pin. Memory Address Bit16, when on-chip tranceiver is used, it is defined as MA16, while in MII mode, it is used as receive data bit RXD3 pin. Memory Data Bit 15-0 : Internal pull-down. 1, MA[19:3] 115-119 7 MA19(RXD0) 6 5 4 MA18(RXD1) MA17(RXD2) MA16(RXD3) 90-96, MD[15:0] 98-104, 106-109 114 MA2(EEDO) 1/O,4ma 113 MA1(EEDI) 1/O,4ma 111 MA0(EECK) 1/O,4ma 87 86 88, 89 P/N:PM0729 MOEB MCSB MWEB[1:0] O,4ma O,4ma O,4ma