Power MOSFET

www.DataSheet4U.com MTD5P06V Preferred Device Power MOSFET 5 Amps, 60 Volts P−Channel DPAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. • Avalanche Energy Specified • IDSS and VDS(on) Specified at Elevated Temperature MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Drain−to−Source Voltage Drain−to−Gate Voltage (RGS = 1.0 MΩ) Gate−to−Source Voltage − Continuous − Non−repetitive (tp ≤ 10 ms) Drain Current − Continuous @ 25°C Drain Current − Continuous @ 100°C Drain Current − Single Pulse (tp ≤ 10 µs) Total Power Dissipation @ 25°C 25°C Derate above 25 C Total Power Dissipation @ TA = 25°C (Note 2.) Operating and Storage Temperature Range Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 5 Apk, L = 10 mH, RG = 25 Ω) Thermal Resistance − Junction to Case − Junction to Ambient (Note 1.) − Junction to Ambient (Note 2.) Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 60 60 ± 15 ± 25 5 4 18 40 0.27 2.1 −55 to 175 125 Unit Vdc Vdc S Vdc Vpk Adc Apk Watts W/°C W/ C Watts °C mJ 1 2 3 DPAK CASE 369C Style 2 4 YWW 5P06V 2 1 3 Drain Gate Source 4 Drain 1 YWW 5P06V 1 2 3 Gate Drain Source Package DPAK DPAK Straight Lead DPAK Shipping 75 Units/Rail 75 Units/Rail 2500 Tape & Reel Publication Order Number: MTD5P06V/D 4 G http://onsemi.com V(BR)DSS 60 V RDS(on) TYP 340 mW ID MAX 5.0 A P−Channel D MARKING DIAGRAMS 4 Drain TJ, Tstg EAS °C/W RθJC RθJA RθJA TL 3.75 100 71.4 260 °C 3 DPAK CASE 369D Style 2 5P06V Y WW Device Code = Year = Work Week 2 1. When surface mounted to an FR4 board using the minimum recommended pad size. 2. When surface mounted to an FR−4 board using the 0.5 sq.in. drain pad size. ORDERING INFORMATION Device NTD5P06V NTD5P06V−1 NTD5P06VT4 Preferred devices are recommended choices for future use and best overall value. © Semiconductor Components Industries, LLC, 2003 1 November, 2003 − Rev. 3 MTD5P06V ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic OFF CHARACTERISTICS Drain−Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C) Gate−Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 3.) Gate Threshold Voltage (VDS = VGS, ID = 250 µAdc) Threshold Temperature Coefficient (Negative) Static Drain−Source On−Resistance (VGS = 10 Vdc, ID = 2.5 Adc) Drain−Source On−Voltage (VGS = 10 Vdc, ID = 5 Adc) (VGS = 10 Vdc, ID = 2.5 Adc, TJ = 150°C) Forward Transconductance (VDS = 15 Vdc, ID = 2.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 4.) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Gate Charge (See Figure 8) (S Fi (VDS = 48 Vdc, ID = 5 Adc, VGS = 10 Vdc) (VDD = 30 Vdc, ID = 5 Adc, VGS = 10 Vdc, Vdc RG = 9.1 Ω) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (IS = 5 Adc, VGS = 0 Vdc) (IS = 5 Adc, VGS = 0 Vdc, TJ = 150°C) VSD − − trr (IS = 5 Adc VGS = 0 Vdc, Adc, Vdc dIS/dt = 100 A/µs) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25″ from package to center of die) Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) 3. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperature. LD − LS − 7.5 − 4.5 − nH nH ta tb QRR − − − − 1.72 1.34 97 73 24 0.42 3.5 − − − − − µC ns Vdc − − − − − − − − 11 26 17 19 12 3.0 5.0 5.0 20 50 30 40 20 − − − nC ns (VDS = 25 Vdc, VGS = 0 Vdc, Vd Vd f = 1.0 MHz) Ciss Coss Crss − − − 367 140 29 510 200 60 pF VGS(th) 2.0 − RDS(on) VDS(on) − − gFS 1.5 3.6 − − − 2.7 2.6 Mhos − 2.8 4.7 0.34 4.0 − 0.45 Vdc mV/°C Ohm Vdc V(BR)DSS 60 − IDSS − − IGSS − − − − 10 100 100 nAdc − 61.2 − − Vdc mV/°C µAdc Symbol Min Typ Max Unit Reverse Recovery Time http://onsemi.com 2 MTD5P06V TYPICAL ELECTRICAL CHARACTERISTICS 10 VGS = 10V I D , DRAIN CURRENT (AMPS) 8 TJ = 25°C 6V 9V 10 7V I D , DRAIN CURRENT (AMPS) 9 8 7 6 5 4 3 2 1 9 0 2 3 4 5 6 7 8 8V VDS ≥ 10 V TJ = −55°C 25°C 100°C 6 4 5V 2 4V 0 0 1 2 3 4 5 6 7 8 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS) R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS) Figure 2. Transfer Characteristics 0.6 0.55 0.5 0.45 0.4 0.35 0.3 0.25 0.2 1 2 3 4 5 6 7 ID, DRAIN CURRENT (AMPS) 8 9 10 − 55°C 25°C VGS = 10 V TJ = 100°C 0.4 TJ = 25°C VGS = 10 V 0.35 0.3 15 V 0.25 0.2 1 2 3 4 5 7 6 ID, DRAIN CURRENT (AMPS) 8 9 10 Figure 3. On−Resistance versus Drain Current and Temperature Figure 4. On−Resistance versus Drain Current and Gate Voltage RDS(on) , DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 −50 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) 150 175 I DSS , LEAKAGE (nA) VGS = 10 V ID = 2.5 A 100 VGS = 0 V 10 TJ = 125°C 1 0 50 10 20 30 40 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 60 Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−To−Source Leakage Current versus Voltage http://onsemi.com 3 MTD5P06V POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG − VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) 1000 900 800 C, CAPACITANCE (pF) 700 600 500 400 300 200 100 0 10 VGS = 0 V 5 VGS 0 VDS 5 Crss 10 15 20 25 Coss Ciss Crss Ciss VDS = 0 V The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. TJ = 25°C GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation http://onsemi.com 4 MTD5P06V VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 10 9 8 7 6 5 4 3 2 1 0 0 2 4 6 Q3 VDS 8 10 TJ = 25°C ID = 5 A 12 Q1 Q2 QT VGS 60 54 48 42 36 30 24 18 12 6 0 14 100 TJ = 25°C ID = 5 A VDD = 30 V VGS = 10 V t, TIME (ns) td(off) 10 tf td(on) VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS) tr 1 1 10 RG, GATE RESISTANCE (OHMS) 100 Qg, TOTAL GATE CHARGE (nC) Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN−TO−SOURCE DIODE CHARACTERISTICS 5 4.5 I S , SOURCE CURRENT (AMPS) 4 3.5 3 2.5 2 1.5 1 0.5 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 TJ = 25°C VGS = 0 V VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 10. Diode Forward Voltage