ISO2-CMOS ST-BUS FAMILY Digital Subscriber Interface Circuit Digital Network Interface Circuit

® ISO2-CMOS ST-BUS™ FAMILY MT9171/72 Digital Subscriber Interface Circuit Digital Network Interface Circuit Features • • • • • • • • • Full duplex transmission over a single twisted pair Selectable 80 or 160 kbit/s line rate Adaptive echo cancellation Up to 3km (9171) and 4 km (9172) ISDN compatible (2B+D) data format Transparent modem capability Frame synchronization and clock extraction MITEL ST-BUS compatible Low power (typically 50 mW), single 5V supply ISSUE 1 May 1995 Ordering Information MT9171AE 22 Pin Plastic DIP MT9172AE 22 Pin Plastic DIP MT9172AC 22 Pin Ceramic DIP MT9171AN 24 Pin SSOP MT9172AN 24 Pin SSOP MT9171AP 28 Pin PLCC MT9172AP 28 Pin PLCC -40°C to + 85°C a twisted wire pair. They use adaptive echocancelling techniques and transfer data in (2B+D) format compatible to the ISDN basic rate. Several modes of operation allow an easy interface to digital telecommunication networks including use as a high speed limited distance modem with data rates up to 160 kbit/s. Both devices function identically but with the DSIC having a shorter maximum loop reach specification. The generic "DNIC" will be used to reference both devices unless otherwise noted. The MT9171/72 is fabricated in Mitel’s ISO2-CMOS process. Applications • • • • Digital subscriber lines High speed data transmission over twisted wires Digital PABX line cards and telephone sets 80 or 160 kbit/s single chip modem Description The MT9171 (DSIC) and MT9172 (DNIC) are multifunction devices capable of providing high speed, full duplex digital transmission up to 160 kbit/s over DSTi/Di CDSTi/ CDi Transmit Interface Prescrambler Scrambler Differentially Encoded Biphase Transmitter Transmit Filter & Line Driver LOUT F0/CLD C4/TCK F0o/RCK MS0 MS1 MS2 RegC Control Register Transmit Timing VBias Address Echo Canceller Error Signal Echo Estimate — DPLL MUX LOUT DIS Master Clock Phase Locked Transmit/ Clock Receive Timing & Control Sync Detect Status Receive Precan ∑ + Receive Filter -1 +2 LIN OSC2 DSTo/Do CDSTo/ CDo Receive Interface DePrescrambler Descrambler Differentially Encoded Biphase Receiver OSC1 VDD VSS VBias VRef Figure 1 - Functional Block Diagram 9-133 MT9171/72 Advance Information LOUT VBias VRef MS2 MS1 MS0 RegC F0/CLD CDSTi/CDi CDSTo/CDo VSS 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 VDD LIN TEST LOUT DIS Precan OSC1 OSC2 C4/TCK F0o/RCK DSTi/Di DSTo/Do 4 3 2 1 28 27 26 • VRef VBias LOUT NC VDD LIN TEST 22 PIN PDIP/CERDIP LOUT VBias VRef MS2 MS1 MS0 RegC NC F0/CLD CDSTi/CDi CDSTo/CDo VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 PIN SSOP 24 23 22 21 20 19 18 17 16 15 14 13 VDD LIN TEST LOUT DIS Precan OSC1 NC OSC2 C4/TCK F0o/RCK DSTi/Di DSTo/Do Figure 2 - Pin Connections Pin Description Pin # 22 1 2 3 24 1 2 3 28 2 3 4 5,7, 8 9 10 Name LOUT VBias VRef Description Line Out. Transmit Signal output (Analog). Referenced to VBias. Internal Bias Voltage output. Connect via 0.33 µF decoupling capacitor to VDD. Internal Reference Voltage output. Connect via 0.33 µF decoupling capacitor to VDD. 4,5, 4,5, 6 6 7 8 7 9 MS2-MS0 Mode Select inputs (Digital). The logic levels present on these pins select the various operating modes for a particular application. See Table 1 for the operating modes. RegC F0/CLD Regulator Control output (Digital). A 512 kHz clock used for switch mode power supplies. Unused in MAS/MOD mode and should be left open circuit. Frame Pulse/C-Channel Load (Digital). In DN mode a 244 ns wide negative pulse input for the MASTER indicating the start of the active channel times of the device. Output for the SLAVE indicating the start of the active channel times of the device. Output in MOD mode providing a pulse indicating the start of the Cchannel. Control/Data ST-BUS In/Control/Data In (Digital). A 2.048 Mbit/s serial control & signalling input in DN mode. In MOD mode this is a continuous bit stream at the bit rate selected. Control/Data ST-BUS Out/Control/Data Out (Digital). A 2.048 Mbit/s serial control & signalling output in DN mode. In MOD mode this is a continuous bit stream at the bit rate selected. 9 10 12 CDSTi/ CDi CDSTo/ CDo 10 11 13 9-134 CDSTi/CDi CDSTo/CDo VSS DSTo/Do DSTi/Di F0o/RCK NC 12 13 14 15 16 17 18 MS2 NC MS1 MS0 RegC F0/CLD NC 5 6 7 8 9 10 11 25 24 23 22 21 20 19 NC LOUT DIS Precan OSC1 OSC2 NC C4/TCK 28 PIN PLCC Advance Information Pin Description (continued) Pin # 22 11 12 13 14 24 12 13 14 15 28 14 15 16 17 Name VSS Negative Power Supply (0V). Description MT9171/72 DSTo/Do Data ST-BUS Out/Data Out (Digital). A 2.048 Mbit/s serial PCM/data output in DN mode. In MOD mode this is a continuous bit stream at the bit rate selected. DSTi/Di Data ST-BUS In/Data In (Digital). A 2.048 Mbit/s serial PCM/data input in DN mode. In MOD mode this is a continuous bit stream at the bit rate selected. F0o/RCK Frame Pulse Out/Receive Bit Rate Clock output (Digital). In DN mode a 244 ns wide negative pulse indicating the end of the active channel times of the device to allow daisy chaining. In MOD mode provides the receive bit rate clock to the system. C4/TCK Data Clock/Transmit Baud Rate Clock (Digital). A 4.096 MHz TTL compatible clock input for the MASTER and output for the SLAVE in DN mode. For MOD mode this pin provides the transmit bit rate clock to the system. Oscillator Output. CMOS Output. Oscillator Input. CMOS Input. D.C. couple signals to this pin. Refer to D.C. Electrical Characteristics for OSC1 input requirements. Precanceller Disable. When held to Logic ’1’, the internal path from LOUT to the precanceller is forced to VBias thus bypassing the precanceller section. When logic ’0’, the LOUT to the precanceller path is enabled and functions normally. An internal pulldown (50 kΩ) is provided on this pin. No Connection. Leave open circuit 15 16 19 16 17 18 17 19 20 21 22 23 OSC2 OSC1 Precan 8, 18 1,6, 11, 18, 20, 25 24 NC 19 21 LOUT DIS LOUT Disable. When held to logic “1”, LOUT is disabled (i.e., output = VBias). When logic “0”, LOUT functions normally. An internal pulldown (50 kΩ) is provided on this pin. TEST LIN VDD Test Pin. Connect to VSS. Receive Signal input (Analog). Positive Power Supply (+5V) input. 20 21 22 22 23 24 26 27 28 9-135 MT9171/72 Advance Information F0 C4 DSTi A AA AAAAA AAAAA A AA AAAAA A AA AAAAA B17 A AA AAAAA A AA AAAAA A AA AAAAA AAAAA AA AA A AAAA AA A AAAA AA A AAAA AA A B17 AAAA AA AA AAAA AA A AAAA A AAAA AA A AAAAAA AAAA B16 B15 B14 B13 B12 B11 B10 AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA B17 AAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA B17 AAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAA DSTo B16 B15 B14 B13 B12 B11 B10 F0o Channel Time 0 Figure 3 - DV Port - 80 kbit/s (Modes 2, 3, 6) F0 C4 DSTi AA AA AAAAAA AA AAAA AA AAAAAA AA AA AAAAAA B17 B16 B15 B14 AA AAAA AA AA AAAAAA AA AAAAAA AAAA AA AA AAAAAA AAAAAA AA AAAA AA AA AAAAAA B17 B16 B15 B14 AA AAAA AA AA AAAAAA AA AAAAAA AAAA AAAAAAAAA AAA AAAA AAAAAAAAAAAAAAAA AA AAAAAAAAA AAA AAAA AAAAAAAAAAAAAAAA AA AAAA AA B13 B12 B11 B10AAAAAAAAA AAA B27 B26 B25 B24 B23 B22 B21 B20AAAAAAAAAAAAAAAA B17 AAAAAAAAA AAA AAAA AAAAAAAAAAAAAAAA AA AAAAAAAAA AAA AAAAAAA AAAAAAAAAAAAAAAA AA AAAAAAAAA AAAA AAAAAAAAAAAAAAAA AA AAAAAAAAA AAA AAAA AAAAAAAAAAAAAAAA AA AAAAAAAAA AAA AAAA AAAAAAAAAAAAAAAA AA AAAA AA B13 B12 B11 B10AAAAAAAAA AAA B27 B26 B25 B24 B23 B22 B21 B20AAAAAAAAAAAAAAAA B17 AAAAAAAAA AAA AAAA AAAAAAAAAAAAAAAA AA AAAAAAAAA AAA AAAAAAA AAAAAAAAAAAAAAAA AA AAAAAAAAA AAAA AAAAAAAAAAAAAAAA AA DSTo F0o Channel Time 0 Channel Time 16 Figure 4 - DV Port - 160 kbit/s (Modes 2, 3, 6) 9-136 Advance Information Functional Description The MT9171/72 is a device which has been designed primarily as an interface for the Integrated Services Digital Network (ISDN). However, it may be used in practically any application that requires high speed data transmission over two wires, including smart telephone sets, workstations, data terminals and computers. In the ISDN, the DNIC is ideal for providing the interface at the U reference point. The device supports the 2B+D channel format (two 64 kbit/s Bchannels and one 16 kbit/s D-channel) over two wires as recommended by the CCITT. The line data is converted to and from the ST-BUS format on the system side of the network to allow for easy interfacing with other components such as the Sinterface device in an NT1 arrangement, or to digital PABX components. Smart telephone sets with data and voice capability can be easily implemented using the MT9171/72 as a line interface. The device’s high bandwidth and long loop length capability allows its use in a wide variety of sets. This can be extended to provide full data and voice capability to the private subscriber by the installation of equipment in both the home and central office or remote concentration equipment. Within the subscriber equipment the MT9171/72 would terminate the line and encode/ decode the data and voice for transmission while additional electronics could provide interfaces for a standard telephone set and any number of data ports supporting standard data rates for such things as computer communications and telemetry for remote meter reading. Digital workstations with a high degree of networking capability can be designed using the DNIC for the line interface, offering up to 160 kbit/s data transmission over existing telephone lines. The MT9171/72 could also be valuable within existing computer networks