Universal Serial Bus Controller

www.DataSheet4U.com Technical Brief O K I A S I C P R O D U C T S W712 Universal Serial Bus Controller 0.5µm Technology Mega Macrofunction January 1997 s s ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– Contents Description................................................................................................................................................................ 1 Features ..................................................................................................................................................................... 1 Signal Descriptions .................................................................................................................................................. 4 Functional Description ............................................................................................................................................ 7 Protocol Engine .................................................................................................................................................. 7 DPLL..................................................................................................................................................................... 7 Timer .................................................................................................................................................................... 7 Status/Control ................................................................................................................................................... 7 FIFO Control ...................................................................................................................................................... 7 Application Interface ......................................................................................................................................... 8 Frame Timer Synthesizer................................................................................................................................... 8 Remote Wakeup.................................................................................................................................................. 8 USB Transfers ..................................................................................................................................................... 8 USB Interface ...................................................................................................................................................... 8 Glossary ..................................................................................................................................................................... 9 Appendix ................................................................................................................................................................. 10 Oki Semiconductor W712 USB Device Controller 0.5µm Technology Mega Macrofunction DESCRIPTION The Universal Serial Bus (USB) Device Controller Mega Macrofunction is a featured element in Oki’s 0.5µm Sea of Gates (SOG) and Customer Structured Array (CSA) families. Oki's USB mega macrofunction provides a USB interface, control/status block, FIFO control, and application interface in two highly integrated submodules for system design interfaces based on the USB protocol. The submodule partitioning allows custom configurations to be easily developed. The USB mega macrofunction connects an industry standard USB interface with a microprocessor-style parallel application interface. This straightforward interface permits easy integration of the USB mega macrofunction to the target application. Using Oki’s USB mega macrofunction, designers can reduce development time, risk, and introduce their USB based products to market faster. Oki’s W712 USB Device Controller mega macrofunction provides a complete USB device interface solution and is fully compliant with the Universal Serial Bus 1.0 specification. For more details on the Universal Serial Bus 1.0 specification, refer to www.usb.org. FEATURES • USB 1.0 compliant • Full-speed (12 Mb/sec) and low-speed (1.5 Mb/sec) support • Microprocessor-style parallel application interface • Supports isochronous, control, interrupt and bulk transfers • Supports four transmit FIFO’s - Three 64 byte - One 2 Kbyte (2-level) • Supports four receive FIFO’s - Three 64 byte - One 2 Kbyte (2-level) • Supports one control endpoint and six additional endpoint addresses • Expandable up to 32 endpoint addresses • Customizable to specific application requirements Supported ASIC Families Family Name MSM13R0000 MSM98R000 Family Type Sea of Gates Customer Structured Array Oki Semiconductor 1 s W712 USB Device Controller s ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– Recommended Operating Conditions (VSS = 0 V) Parameter Power supply voltage Operating temperature Symbol VDD Tj Min. 2.7 -40 Typ. 3.3 +25 Max 3.6 +85 Unit V °C Mega Macrofunction Characteristics Mega Macrofunction W712 Description USB Device Controller Logic Gate Count 15797 Logic Pin Count 139 W712 usb_dpin usb_dmin usb_rxd usb_dpout usb_dmout usb_txenb full_spden sel_ext_pll sys_clock sys_reset testmode mwr_rdb [7:0]ma [7:0]md mrdyb [7:0]pd [3:0]pkt_rdy setup_rdy setup_rdy2 iso_err usb_reset validsof validin validout [7:0]trx_out_data [7:0]rcv_out_data [7:0]trx_in_data [2:0]trx_sel [8:0]trx_wr_ptr [8:0]trx_rd_ptr [6:0]trx_wrb [7:0]rcv_in_data [2:0]rcv_sel [8:0]rcv_wr_ptr [8:0]rcv_rd_ptr [6:0]rcv_wrb osc_clk usb_clk_ext usb_rxd_out USB Interface FIFO Interface DPLL Interface Application Interface Figure 1. Logic Symbol 2 Oki Semiconductor –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– s W712 USB Device Controller s W712 Z712a W712b Clock DPLL Status/Control Application Interface To USB Transceiver Protocol Engine FIFO Control To Application Module To FIFO’s (data path) To FIFO’s (control) To FIFO’s (data path) Figure 2. W712 Block Diagram ASIC W712 Mega Macrofunction Clock DPLL Status/ Control Application Module External Module I/O Optional External DPLL Protocol Engine USB Cable USB Transceiver FIFO Control Application Interface Data Path FIFO(s)/ Data Mux(s) Data Path Figure 3. Example USB Mega Macrofunction Application Oki Semiconductor 3 s W712 USB Device Controller s ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– SIGNAL DESCRIPTIONS USB Interface Signal usb_dpin Type Assertion Description USB Data Plus In. This input and the usb_dmin input are the received single ended data from the USB transceiver. The table below shows values and results for these signals. usb_dpin Input — 0 0 1 1 usb_dmin Input — usb_dmin 0 1 0 1 Result SE0 Logic “0” Logic “1” Undefined USB Data Minus In. This input and the usb_dpin input are the received single ended data from the USB transceiver. See the table for the usb_dpin description, above, for values and results of these signals. USB Data Plus Out. This output and the usb_dmout signal come from the USB transmit engine and drive the differential output buffers. The table below shows values and results for these signals. usb_dpout Output — usb_dpout 0 0 1 1 usb_dmout 0 1 0 1 Result SE0 Logic “0” Logic “1” Undefined usb_dmout Output usb_rxd usb_txenb Output LOW — USB Data Minus Out. This output and the usb_dpout signal come from the USB transmit engine and drive the differential output buffers. See the signal description for usb_dpout, above, for a description of signal values and results. USB Differential Received Data. This input comes from the USB differential receiver, and connects to the W712 mega macrofunction. USB 3-State Output Enable. This signal connects to the transceiver EB input through an inverter gate. When the W712 mega macrofunction asserts this signal LOW, the transceiver transmits data on the USB bus. See Appendix for the USB transceiver Data Sheets. Input — 4 Oki Semiconductor –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– s W712 USB Device Controller s Application Interface Signal sys_clock sys_reset mwr_rdb Input — Type Input Input Assertion — HIGH Description Clock. Attach a 12-MHz clock signal to this input for full-speed operation and 1.5 MHz for low-speed operation. W712 Reset. Asserting this signal HIGH resets the W712 mega macrofunction. The application module is required to assert this signal at power-on. Write/Read Select. When external application logic asserts this signal HIGH, the application is in WRITE mode. When asserted LOW, the application is in READ mode. External application logic asserts this signal HIGH when writing data to the transmit FIFOs or to the register files. External application logic asserts this signal LOW when reading data from the receiving FIFOs or from the register files. The register files contain information describing the function and transaction status. USB Reset. This is the reset signal from the USB device controller. Address Bus. These eight inputs receive the address of the register files in the USB device controller. Input Data Bus. These ei