(MSM13Q / MSM14Q) Sea of Gates Arrays

www.DataSheet4U.com DATA SHEET O K I A S I C P R O D U C T S MSM13Q/14Q000 0.35 µm Sea of Gates Arrays November 1999 s s ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– Oki Semiconductor MSM13Q0000/14Q0000 0.35 µm Sea of Gates Arrays DESCRIPTION Oki’s 0.3 5 µm ASIC products deliver ultra-high performance and high density at low power dissipation. The MSM13Q0000/14Q0000 series devices (referred to as “MSM13Q/14Q”) are implemented with the industry-standard Cell-Based Array (CBA) architecture in a Sea-of-Gates (SOG) structure. Built in a 0.35 µm drawn CMOS technology (with an L-Effective of 0.27 µm), these SOG devices are available in three layers (MSM13Q) and four layers (MSM14Q) of metal. The semiconductor process is adapted from Oki’s production-proven 64-Mbit DRAM manufacturing process. The MSM13Q/14Q Series contains 6 arrays each, offering over 1 million raw gates and 352 I/O pads. Up to 66% and 90% of the raw gates can be used for the 3-layer and 4-layer arrays, respectively. Oki’s 0.35 µm family is optimized for 3-V core operation with optimized 3-V I/O buffers and 5-V tolerant 3-V buffers. These SOG products are designed to fit the most popular plastic quad flat packs (QFPs), thin QFPs (TQFPs) , and plastic ball grid array (PBGA) packages. The MSM13Q/14Q Series uses the popular CBA architecture from Silicon Architects of Synopsys which mixes two types of cells (8-transistor compute cells and 4-transistor drive cells) on the same die to deliver high gate density and high drives. The CBA is supported by a rich macro library, optimized for synthesis. Memory blocks are efficiently created by Oki’s memory compilers to generate single- and dual-port RAM’s in high-density and low-power configurations with synchronous RAM options. As such, the MSM13Q/14Q series is well suited to memory-intensive designs with high production volumes approaching the real estate and cost savings of standard cells. At the same time, its SOG architecture allows rapid prototyping turnaround times. Thus, Oki’s MSM13Q/14Q family offers the best of two worlds: quick prototyping of a gate array and low production cost of a standard cell. Oki’s 0.35 µm ASIC products are supported by leading-edge CAD tools including a synthesis-linked floorplanner, motive static timing analyzer, and H-clock tree methodology. They are further supported by specialized macrocells including phase-locked loop (PLL), pseudo-emitter coupled logic (PECL), peripheral component interconnect (PCI), universal synchronous receiver/transmitter (UART) cells, and ARM7TDMI RISC cores. FEATURES • 0.35 µm drawn 3- and 4-layer metal CMOS • Optimized 3.3-V core • Optimized 3-V I/O and 3-V I/O that is 5-V tolerant • CBA SOG architecture • Over 1.0M raw gates and 352 pads • User-configurable I/O with VSS, VDD, TTL, 3state, and 1- to 24-mA options • Slew-rate-controlled outputs for low-radiated noise • H-clock tree cells which reduce the maximum skew for clock signals • User-configurable single and dual-port; synchronous or asynchronous memories • Specialized macrocells including PLL, PECL, PCI, UART, and ARM7TDMI • Floorplanning for front-end simulation, backend layout controls, and link to synthesis • Joint Test Action Group (JTAG) boundary scan and scan-path ATPG • Support for popular CAE systems, including Cadence, IKOS, Mentor Graphics, Synopsys, Viewlogic, and Zycad Oki Semiconductor 1 s MSM13Q0000/14Q0000 s –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– MSM13Q/14Q FAMILY LISTING MSM13Q/14Q Series 0150 0230 0340 0530 0840 1020 PAD No. 144 176 208 256 320 352 Raw Gate (Gates) 157,192 242,400 346,176 536,400 847,048 1,033,000 Usable Gate M13Q(3LM) 105,319 152,712 204,244 289,656 415,054 475,180 Usable Gate M14Q(4LM) 143,045 208,464 276,941 391,572 567,522 650,790 Raw Gate Row 196 240 288 360 452 500 Column 802 1,010 1,202 1,490 1,874 2,066 ARRAY ARCHITECTURE The primary components of a 0.35 µm MSM13Q/14Q circuit include: • • • • • • • I/O base cells Configurable I/O pads for VDD, VSS, or I/O (optimized 3-V I/O and 3-V I/O that is 5-V tolerant) VDD and VSS pads dedicated to wafer probing Separate power bus for output buffers Separate power bus for internal core logic and input buffers Core base modules containing three compute cells for each drive cell Isolated gate structure for reduced input capacitance and increased routing flexibility Each array has 24 dedicated corner pads for power and ground use during wafer probing, with 4 pads per corner. The arrays also have separate power rings for the internal core functions (VDDC and VSSC) and output drive transistors (VDDO and VSSO). The array architecture uses optimally sized transistors to efficiently implement logic and memory in a metal programmable technology. CBA uses two types of cells: compute cells and drive cells. The compute cell employs four PMOS and four NMOS trasnsistors whose sizes are optimized for logic and memory implementations as shown in Figure 1. The quantity and size of the transistors in a compute cell are carefully selected to maximize the efficiency of most commonly used functions in VLSI design. The drive cell consists of two large PMOS pull-up transistors and two large pull-down transistors. The compute and drive cells are tiled to create a channelless core array, with three comput cells for each drive cell as shown in Figure 2. The 3:1 ratio of compute to drive cells was selected for optimal implementation of emerging applications. Macrocells are created using either compute cells, drive cells, or combinations of compute and drive cells. 2 Oki Semiconductor ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– s MSM13Q0000/14Q0000 s Compute Cell Compute Cell Compute Cell Drive Cell Figure 1. Base Cell Consisting of Three Compute Cells and One Drive Cell Compute Cell Drive Cell Figure 2. Core Array with Base Cell Mirrored Horizontally and Vertically Oki Semiconductor 3 s MSM13Q0000/14Q0000 s –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (VSS = 0 V, Tj = 25°C) [1] Parameter Power supply voltage Input voltage Normal buffers 5-V tolerant Output voltage Normal buffers 5-V tolerant Input current Normal buffers 5-V tolerant Output current per I/O Normal buffers 5-V tolerant Storage temperature Symbol VDD VI VI VO VO II II IO IO Tstg IO = 1, 2, 4, 6, 8, 12, 24 mA IO = 2, 4, 6, 8, 12 mA – Conditions Rated Value -0.3 to +4.6 -0.3 to VDD+0.3 -0.3 to 6.0 -0.3 to VDD+0.3 -0.3 to 6.0 -10 to +10 -6 to +6 -24 to +24 -8 to +8 -65 to +150 Unit V V V mA mA °C 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions in the other specifications of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions (VSS = 0 V) Parameter Power supply voltage Junction temperature Symbol VDD (3 V) Tj Rated Value +3.0 to +3.6 -40 to +85 Unit V °C 4 Oki Semiconductor ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– s MSM13Q0000/14Q0000 s DC Characteristics (VDD = 3.0 to 3.6 V, VSS = 0 V, Tj = -40°C to +85°C) Rated Value Parameter High-level input voltage Normal buffer 5-V tolerant Low-level input voltage Normal buffer 5-V tolerant TTL- level Schmitt trigger input threshold voltage Normal buffer Symbol VIH VIH VIL VIL Vt+ Vt∆Vt 5-V tolerant Vt+ Vt∆Vt High-level output voltage Normal buffer VOH TTL input TTL input TTL input Vt+ - VtTTL 5-V tolerant input Vt+ - VtIOH = -100 µA IOH = -1, -2, -4, -6, -8, -12, -24 mA 5-V tolerant VOH IOH = -100 µA IOH = -1, -2, -4, -6, -8, -12 mA Low-level output voltage Normal buffer VOL IOL = 100 µA IOL = 1, 2, 4, 6, 8, 12, 24mA 5-V tolerant VOL IOL = 100 µA IOL = 1, 2, 4, 6, 8, 12 mA High-level input current Normal buffer IIH VIH = VDD VIH = VDD (50-kΩ pull-down) 5-V tolerant IIH VIH = VDD VIH = VDD (50-kΩ pull-down) Low-level input current Normal buffer IIL VIL = VSS VIL = VSS (50-kΩ pull-up) VIL = VSS (3-kΩ pull-up) 5-V tolerant 3-state output leakage current Normal buffer IIL IOZH VIL = VSS VOH = VDD VOH = VDD (50-kΩ pull-down) IOZL VOL = VSS VOL = VSS (50-kΩ pull-up) VOL = VSS (3-kΩ pull-up) 5-V tolerant IOZH VOH = VDD VOH = VDD (50-kΩ pull-down) IOZL Stand-by current [3] [1] Conditions Min. 2.0 2.0 -0.3 -0.3 – 0.7 0.4 – 0.7 0.4 VDD - 0.2 2.4 VDD - 0.2 2.4 – – – – – 10 – 10 -10 -200 -3.3 -10 – 10 -10 -200 -3.3 – 10 -10 Typ – – – – [2] Max. VDD + 0.3 5.5 0.8 0.8 2.0 – – 2.0 – – – – – – 0.2 0.4 0.2 0.4 10 200 10 200 -10 -0.3 – 10 200 – -10 -0.3 10 200 – Unit 1.5 1.0 0.5 1.5 1.0 0.5 – – – – – – – – 0.1 66 0.1 66 -0.1 -66 -1.1 -0.1 0.1 -66 -0.1 -66 -1.1 0.1 66 -0.1 Design Dependent V µA mA µA µA mA µA VOL = VSS Output open, VIH = VDD, VIL = VSS IDDQ µA 1. JEDEC Compatible; JESD8-1A LVTTL. 2. Typical condition is VDD = 3.3 V and Tj = 25oC on a typical process. 3. RAM/ROM should be in powerdown mo