Description
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low Voltage PLL Clock Driver The MPC950/951 are 3.3V compatible, PLL based clock driver devices targeted for high performance clock tree designs. With output frequencies of up to 180MHz and output skews of 375ps the MPC950 is ideal for the most demanding clock tree designs. The devices employ a fully differential PLL design to minimize cycle–to–cycle and long term jitter. This parameter is of significant importance when the clock driver is providing the reference clock for PLL’s on board today’s microprocessors and ASiC’s. The devices offer 9 low skew outputs, the outputs are configurable to support the clocking needs of the various high performance microprocessors. www.DataSheet4U.com MPC950 MPC951 LOW VOLTAGE PLL CLOCK DRIVER • Fully Integrated PLL • Oscillator or Crystal Reference Input • Output Frequency up to 180MHz • Outputs Disable in High Impedance • Compatible with PowerPC™, Intel and High Performance RISC Microprocessors • TQFP Packaging • Output Frequency Configurable • ±100ps Typical Cycle–to–Cycle Jitter FA SUFFIX 32–LEAD TQFP PACKAGE CASE 873A–02 Two selectable feedback division ratios are available on the MPC950 to provide input reference clock flexibility. The FBSEL pin will choose between a divide by 8 or a divide by 16 of the VCO frequency to be compared with the input reference to the MPC950. The internal VCO is running at either 2x or 4x the high speed output, depending on configuration, so that the input reference will be either one half, one fourth or one eighth the high speed output. The MPC951 replaces the crystal oscillator and internal feedback of the MPC950 with a differential PECL reference input and an external feedback input. These features allow for the MPC951 to be used as a zero delay, low skew fanout buffer. In addition, the external feedback allows for a wider variety of input–to–output frequency relationships. The MPC951 REF_SEL pin allows for the selection of an alternate LVCMOS input clock to be used as a test clock or to provide the reference for the PLL from an LVCMOS source. The MPC950 provides an external test clock input for scan clock distribution or system diagnostics. In addition the REF_SEL pin allows the user to select between a crystal input to an on–board oscillator for the reference or to chose a TTL level oscillator input directly. The on–board crystal oscillator requires no external components beyond a series resonant crystal. Both the MPC950 and MPC951 are fully 3.3V compatible and require no external loop filter components. All inputs accept LVCMOS or LVTTL compatible levels while the outputs provide LVCMOS levels with the capability to drive terminated 50Ω transmission lines. Select inputs do not have internal pull–up/pull–down resistors and thus must be set externally. If the PECL_CLK inputs are not used, they can be left open. For series terminated 50Ω lines, each of the MPC950/951 outputs can drive two traces giving the device an effective fanout of 1:18. The device is packaged in a 7x7mm 32–lead TQFP package to provide the optimum combination of board density and performance. PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation. 2/97 © Motorola, Inc. 1997 1 REV 4 MPC950 MPC951 MPC950 LOGIC DIAGRAM fsela PLL_En Tclk Ref_Sel xtal1 xtal2 xtal OSC PHASE DETECTOR VCO 200–480MHz ÷2/÷4 Qa LPF www.DataSheet4U.com FBsel fselb (Pull Down) ÷4/÷8 Qb ÷8/÷16 Qc0 Qc1 fselc MR/OE POWER–ON RESET ÷4/÷8 Qd0 Qd1 fseld Qd2 Qd3 Qd4 ÷4/÷8 GNDO GNDO VCCO VCCO Qd0 Qd1 Qc0 Qc1 FUNCTION TABLES Ref_Sel Function TCLK XTAL_OSC Function PLL Enabled PLL Bypass Function ÷8 ÷16 Function Outputs Disabled Outputs Enabled Function Qa = ÷4; Qb:d = ÷8 Qa = ÷2; Qb:d = ÷4 24 GNDO Qb VCCO Qa GNDO TCLK PLL_En Ref_Sel 25 26 27 28 23 22 21 20 19 18 17 16 15 14 13 Qd2 VCCO Qd3 GNDO 1 0 PLL_En 1 0 FBsel MPC950 29 30 31 32 1 2 3 4 5 6 7 8 12 11 10 9 Qd4 VCCO MR/OE xtal2 1 0 MR/OE 1 0 fseln 1 0 VCCA GNDI fsela fselb fseld MOTOROLA FBsel xtal1 fselc 2 TIMING SOLUTIONS BR1333 — Rev 6 MPC950 MPC951 MPC951 LOGIC DIAGRAM fsela PLL_En Tclk Ref_Sel PECL_CLK PECL_CLK (Pull Up) PHASE DETECTOR VCO 200–550MHz ÷2/÷4 Qa LPF www.DataSheet4U.com Ext_FB fselb (Pull Down) ÷4/÷8 Qb ÷4/÷8 Qc0 Qc1 fselc MR/OE POWER–ON RESET ÷4/÷8 Qd0 Qd1 fseld Qd2 Qd3 Qd4 GNDO GNDO VCCO VCCO Qd0 Qd1 Qc0 Qc1 FUNCTION TABLES 24 GNDO Qb VCCO Qa GNDO TCLK PLL_En Ref_Sel 25 26 27 28 23 22 21 20 19 18 17 16 15 14 13 Qd2 VCCO Qd3 GNDO Qd4 VCCO MR/OE PECL_CLK Ref_Sel 1 0 PLL_En 1 0 MR/OE 1 0 fseln 1 0 PECL_CLK VCCA Ext_FB GNDI fsela fselb fseld fselc Function TCLK PECL_CLK Function PLL Enabled PLL Bypass Function Outputs Disabled Outputs Enabled Function Qa = ÷4; Qb:d = ÷8 Qa = ÷2; Qb:d = ÷4 MPC951 29 30 31 32 1 2 3 4 5 6 7 8 12 11 10 9 TIMING SOLUTIONS BR1333 — Rev 6 3 MOTOROLA MPC950 MPC951 FUNCTION TABLE – MPC950/951 INPUTS fsela fselb fselc fseld Qa(1) 2x 2x 2x 2x 2x 2x 2x 2x x x x x x x x x OUTPUTS Qb(1) x x x x x/2 x/2 x/2 x/2 x x x x x/2 x/2 x/2 x/2 Qc(2) x x x/2 x/2 x x x/2 x/2 x x x/2 x/2 x x x/2 x/2 Qd(5) x x/2 x x/2 x x/2 x x/2 x x/2 x x/2 x x/2 x x/2 Total 2x 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 TOTALS Total x 8 3 6 1 7 2 3 0 9 4 7 2 8 3 6 1 Total x/2 0 5 2 7 1 6 5 8 0 5 2 7 1 6 3 8 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 www.DataSheet4U.com 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 NOTE: x = fVCO/4; 200MHz < fVCO < 480MHz. ABSOLUTE MAXIMUM RATINGS* Symbol VCC VI IIN TStor Supply Voltage Input Voltage Input Current Storage Temperature Range –40 Parameter Min –0.3 –0.3 Max 4.6 VDD + 0.3 ±20 125 Unit V V mA °C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied. DC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%) Symbol VIH VIL VPP VCMR VOH VOL IIN CIN Cpd ICC Characteristic Input HIGH Voltage Input LOW Voltage Peak–to–Peak Input Voltage Common Mode Range Output HIGH Voltage Output LOW Voltage Input Current Input Capacitance Power Dissipation Capacitance Maximum Quiescent Supply Current 25 90 115 LVCMOS Inputs LVCMOS Inputs PECL_CLK PECL_CLK 300 VCC–2.0 2.4 0.5 ±120 4 Min 2.0 Typ Max 3.6 0.8 1000 VCC–0.6 Unit V V mV mV V V µA pF pF mA Per Output All VCC Pins Note 1. IOH = –40mA, Note 2. IOL = 40mA, Note 2. Condition ICCPLL Maximum PLL Supply Current 15 20 mA VCCA Pin Only 1. VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “HIGH” input is within the VCMR range and the input swing lies within the VPP specification. 2. The MPC950/951 outputs can drive series or parallel terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge (see Applications Info section). MOTOROLA 4 TIMING SOLUTIONS BR1333 — Rev 6 MPC950 MPC951 PLL INPUT REFERENCE CHARACTERISTICS (TA = 0 to 70°C) Symbol tr, tf fref fXtal frefDC Characteristic TCLK Input Rise/Falls Reference Input Frequency Crystal Oscillator Frequency Reference Input Duty Cycle Note 1. 10 25 Min Max 3.0 Note 1. 25 75 Unit ns MHz MHz % Note 2. Condition 1. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider for the TCLK or PECL_CLK inputs. 2. See Applications Info section for more crystal information. AC CHARACTERISTICS (TA = 0°C to 70°C, VCC = 3.3V ±5%) Symbol www.DataSheet4U.com tr, tf tpw tsk(O) Characteristic Output Rise/Fall Time Output Duty Cycle Output–to–Output Skews Same Frequencies Different Frequencies Qafmax < 150MHz Qafmax > 150MHz fVCO PLL VCO Lock Range Maximum Output Frequency Input to Ext_FB Delay (Note 1.) Output Disable Time Output Enable Time Cycle–to–Cycle Jitter (Peak–to–Peak) Maximum PLL Lock Time ±100 10 Feedback = VCO/4 Feedback = VCO/8 Feedback = VCO/16 Qa (÷2) Qa/Qb (÷4) Qb (÷8) TCLK PECL_CLK 50 –950 250 –770 200 200 200 Min 0.10 tCYCLE/2–1000 200 325 Typ Max 1.0 tCYCLE/2+1000 375 500 750 480 480 480 180 120 60 400 –600 7 6 MHz MPC951 MPC950 or 951 MPC950 Unit ns ps ps Condition 0.8 to 2.0V fmax MHz tpd tPLZ,HZ tPZL tjitter tlock ps ns ns ps ms fref = 50MHz Feedback=VCO/8 Note 2. 1. The specification is guaranteed for the MPC951 only. The tpd window is specified for a 50Mhz input reference clock. The window will enlarge/reduce proportionally from the minimum limits with an increase/decrease of the input reference clock period. 2. See Applications Info section for more jitter information. APPLICATIONS INFORMATION Programming the MPC950/951 The MPC950/951 clock driver outputs can be configured into several frequency relationships, in addition the external feedback option of the MPC951 allows for a great deal of flexibility in establishing unique input to output frequency relationships. The output dividers for the four output groups allows the user to configure the outputs into 1:1, 2:1, 4:1 and 4:2:1 frequency ratios. The use of even dividers ensures that the output duty cycle is always 50%. Table 1 illustrates the various output configurations, the table describes the outputs using the VCO frequency as a reference. As an example for a 4:2:1 relationship the Qa outputs would be set at VCO/2, the Qb’s and Qc’s at VCO/4 and the Qd’s at VCO/8. These settings will provide output frequencies with a 4:2:1 relationship. The division settings establish the output relationship, but one must still ensure that the VCO will be stable given the frequency of the outputs desired. The feedback frequency should be used to situate the VCO into a frequency range in which the PLL will be stable. The design of the PLL is such that for o

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