PowerQUICC II

www.DataSheet4U.com Freescale Semiconductor, Inc. Advance Information MPC8250TS/D Rev. 0.1, 11/2001 MPC8250 PowerQUICC ™ II Technical Summary Freescale Semiconductor, Inc... The MPC8250 PowerQUICC II is a versatile communications processor that integrates a high-performance G2 microprocessor, a flexible system integration unit, and many communications peripheral controllers that can be used in a variety of applications, particularly in communications and networking systems. The MPC8250 is a Footprint-compatible, lower-cost version of the MPC8260. The core is an embedded variant of the 603e microprocessor, referred to as the G2 core, with 16 Kbytes of instruction cache, 16 Kbytes of data cache, and a floating-point unit (FPU). The system interface unit (SIU) consists of a flexible memory controller that interfaces to almost any user-defined memory system and many other peripherals, making this device a complete system on a chip. The communications processor module (CPM) includes all the peripherals found in the MPC860, with the addition of three high-performance communications channels that support 10/100 Ethernet, Transparent, and HDLC. The MPC8250 has dedicated hardware that can handle up to 128 full-duplex, time-division-multiplexed logical channels. This document describes the functional operation of the MPC8250, with an emphasis on peripheral functions. Additional information about the G2 microprocessor core can be found in the MPC603e RISC Microprocessor User’s Manual, REV 3 (order number: MPC603EUM/AD). 1.1 • Features G2 dual-issue integer core — A core version of the MPC603e microprocessor — System core microprocessor supporting frequencies of 150–200 MHz — Separate 16-Kbyte data and instruction caches: – Four-way set associative – Physically addressed – LRU replacement algorithm — PowerPC architecture-compliant memory management unit (MMU) — Common on-chip processor (COP) test interface — High-performance (4.4–5.1 SPEC95 benchmark at 200 MHz; 280 Dhrystones MIPS at 200 MHz) The following is an overview of the MPC8250 feature set: For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Features • • • • Freescale Semiconductor, Inc... • • — Supports bus snooping for cache coherency — Floating-point unit (FPU) Low-power (less than 2.0 W in HiP4) See the MPC8260 Power Consumption Calculator on the Smart Networks Web Page for the 8260 Family at www.motorola.com. Separate power supply for internal logic (1.8 V in HiP4) and for I/O (3.3 V) Separate PLLs for G2 core and for the CPM — G2 core and CPM can run at different frequencies for power/performance optimization — Internal G2 core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios — Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios 64-bit data and 32-bit address 60x bus — Bus supports multiple master designs — Supports single- and four-beat burst transfers — 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller — Supports data parity or ECC and address parity 32-bit data and 18-bit address local bus — Single-master bus, supports external slaves — Eight-beat burst transfers — 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller System interface unit (SIU) — Clock synthesizer — Reset controller — Real-time clock (RTC) register — Periodic interrupt timer — Hardware bus monitor and software watchdog timer — IEEE 1149.1 JTAG test access port — PCI – PCI Specification Revision 2.2 compliant and supports frequencies up to 66 MHz – Support for PCI to G2 memory and G2 memory to PCI streaming – PCI Host Bridge or Peripheral capabilities – Includes 4 DMA channels for PCI/G2 to G2/PCI transfers – Includes all of the configuration registers required by the PCI standard as well as message and doorbell registers – Supports the I 2 O standard – A hot-swap friendly device (supports the Hot Swap Specification as defined by PICMG 2.1 R1.0 August 3, 1998) – Support for 66 MHz, 3.3 V specification – 60x-PCI bus core logic which uses a buffer pool to allocate buffers for each port. – The PCI bridge makes use of the local bus signals, so there is no need for additional pins. • Twelve-bank memory controller 2 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Features • • — Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other userdefinable peripherals — Byte write enables and selectable parity generation — 32-bit address decodes with programmable bank size — Three user programmable machines, general-purpose chip-select machine, and page-mode pipeline SDRAM machine — Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local) — Dedicated interface logic for SDRAM Disable CPU mode Communications processor module (CPM) — Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support for communications peripherals — Interfaces to G2 core through on-chip 24-Kbyte dual-port RAM and DMA controller — Serial DMA channels for receive and transmit on all serial channels — Parallel I/O registers with open-drain and interrupt capability — Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers — Three fast communications controllers supporting the following protocols: – 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent interface (MII) – Transparent – HDLC—Up to T3 rates (clear channel) — A multichannel controller (MCC2) – The MCC handles 128 serial, full-duplex, 64-Kbps data channels. The MCC can be split into four subgroups of 32 channels each. – Almost any combination of subgroups can be multiplexed to single or multiple TDM interfaces — Four serial communications controllers (SCCs) identical to those on the MPC860, supporting the digital portions of the following protocols: – Ethernet/IEEE 802.3 CDMA/CS – HDLC/SDLC and HDLC bus – Universal asynchronous receiver transmitter (UART) – Synchronous UART – Binary synchronous (BISYNC) communications – Transparent — Two serial management controllers (SMCs), identical to those of the MPC860 – Provide management for BRI devices as general circuit interface (GCI) controllers in timedivision-multiplexed (TDM) channels – Transparent – UART (low-speed operation) — One serial peripheral interface identical to the MPC860 SPI — One I2C controller (identical to the MPC860 I2C controller) – Microwire compatible Freescale Semiconductor, Inc... MOTOROLA For More Information On This Product, Go to: www.freescale.com 3 Freescale Semiconductor, Inc. MPC8250 Architecture Overview – Multiple-master, single-master, and slave modes — Up to four TDM interfaces – Supports one group of four TDM channels – 2,048 bytes of SI RAM – Bit or byte resolution – Independent transmit and receive routing, frame synchronization – Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN primary rate, Motorola interchip digital link (IDL), general circuit interface (GCI), and user-defined TDM serial interfaces — Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs, SCCs, SMCs, and serial channels — Four independent 16-bit timers that can be interconnected as two 32-bit timers Freescale Semiconductor, Inc... 1.2 • • • MPC8250 Architecture Overview A 64-bit G2 core derived from the MPC603e with MMUs and cache A system interface unit (SIU) A communications processor module (CPM) As shown in Figure 1, the MPC8250 has three major functional blocks: 4 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MPC8250 Architecture Overview 16-Kbyte Instruction Cache IMMU G2 Core Bus Interface Unit 16-Kbyte Data Cache DMMU 60x-to-PCI Bus Bridge 60x-to-Local Bus Bridge Memory Controller Clock Counter PCI/ Local Bus 60x Bus Freescale Semiconductor, Inc... Timers Parallel I/O Baud Rate Generator Interrupt Controller 32-Kbyte Dual Port RAM Serial DMAs System Functions 4 Virtual IDMAs 32-Bit RISC Communications Processor (CP) and Program ROM MCC2 FCC1 FCC2 FCC3 SCC1 SCC2 SCC3 SCC4 SMC1 SMC2 SPI I2C Time Slot Assigner Serial Interface 4 TDMs 3 MIIs Non-Multiplexed I/O Figure 1. MPC8250 Block Diagram The MPC8250 has two external buses to accommodate bandwidth requirements from the high-speed system core and the very fast communications channels. Both the system core and the CPM have an internal PLL, which allows independent optimization of the frequencies at which they run. The system core and CPM are both connected to the 60x bus. 1.2.1 The G2 Core The G2 core is derived from the 603e microprocessor without the floating-point unit and with power management modifications. The core is a high-performance low-power implementation of the 60x family of reduced instruction set computer (RISC) microprocessors. The G2 core implements the 32-bit portion of the PowerPC architecture, which provides 32-bit effective addresses and integer data types of 8, 16, and 32 bits. The G2 cache provides snooping to ensure data coherency with other masters. This helps ensure coherency between the CPM and system core. The core includes 16 Kbytes of instruction cache and 16 Kbytes of data cache. It has a 64-bit split-transaction external data bus which is connected directly to the external MPC8250 pins. The G2 core has an internal common on-chip (COP) debug processor. This processor allows access to internal scan chains for debugging purposes. It is also used as a serial connection to the core for emulator support. MOTOROLA For More Information On This Product, Go to: www.freescale.com 5 Freescale Semiconductor, Inc. MPC8250 Arch