Leader

www.DataSheet4U.com The FPOA™ Leader Field Programmable Object Array™ Arrix™ Family Product Data Sheet www.mathstar.com 10.26.2006 www.DataSheet4U.com Notice of Liability Information in this document is provided in relationship with MathStar™ products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document except as provided in MathStar's Terms and Conditions of Sale for such products. MathStar may make any changes to specifications and product descriptions at any time, without notice. Copyright Notice Copyright © 2003 - 2006 by MathStar, Inc. All rights reserved. Any reproduction of these materials without the prior written consent of MathStar, Inc. is strictly prohibited. Trademarks MathStar, Field Programmable Object Array, FPOA, and Arrix are trademarks of MathStar, Incorporated. All other trademarks, product names, trade names, and service names are the property of their respective owners. For customer support, visit www.mathstar.com or email us at support@mathstar.com. Published in the United States of America. Arrix Family Data Sheet www.DataSheet4U.com Table of Contents Table of Contents About this Document - - - - - - - - - - - - - - - - - - - - 7 Intended Audience ..................................................................... 7 Related Documents ................................................................... 7 Chapter 1: Introduction - - - - - - - - - - - - - - - - - - - 9 General Description ................................................................... 9 FPOA Architecture ................................................................... 10 Chapter 2: XRAM Hardware - - - - - - - - - - - - - - - - - 13 Overview .................................................................................. 13 External Pins............................................................................ 14 Length and Routing Recommendations . . . . . . . . . . . . . . . . 21 Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Timing Characteristics ............................................................. 26 RLDRAM Details ...................................................................... 31 Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Bank Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Refresh Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Chapter 3: GPIO Hardware- - - - - - - - - - - - - - - - - - 35 Overview .................................................................................. 35 External Pins............................................................................ 36 Timing Characteristics ............................................................. 41 Chapter 4: RX Hardware - - - - - - - - - - - - - - - - - - - 43 Overview .................................................................................. 43 External Pins............................................................................ 44 Matched Lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Timing Characteristics ............................................................. 48 Chapter 5: TX Hardware - - - - - - - - - - - - - - - - - - - 51 Overview .................................................................................. 51 External Pins............................................................................ 52 Matched Lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Timing Characteristics ............................................................. 57 Chapter 6: Initialization and Control - - - - - - - - - - - - - 61 Overview .................................................................................. 61 External Pins............................................................................ 62 PROM Load Sequence ............................................................ 65 www.mathstar.com Arrix Family Field Programmable Object Array (FPOA) 1 Arrix Family Data Sheet Table of Contents www.DataSheet4U.com Initialization and Reset Sequence............................................ Breakpoint Behavior................................................................. Timing Considerations ............................................................. Supported JTAG and PROM Products .................................... JTAG Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PROM Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 7: Electrical Characteristics - - - - - - - - - - - Overview .................................................................................. Power Supply Requirements.................................................... Absolute Minimum and Maximum Ratings............................... Operating Conditions ............................................................... PLL Power Characteristics....................................................... Power Sequencing ................................................................... Power-up Reset ....................................................................... Decoupling Capacitors ............................................................. Current Fluctuations During Initialization ................................. External Pins ............................................................................ Chapter 8: Clock Characteristics - - - - - - - - - - - - - Core Reference Clock Characteristics ..................................... XRAM Clock Characteristics .................................................... GPIO Clock Characteristics ..................................................... RX Clock Characteristics ......................................................... TX Clock Characteristics.......................................................... PROM Clock Characteristics.................................................... Chapter 9: Thermal Considerations- - - - - - - - - - - - General Considerations ........................................................... Junction Temperature .............................................................. Definition of Terms ................................................................... Forced Convection ................................................................... Natural Convection................................................................... Chapter 10: Packaging Information - - - - - - - - - - - - Overview .................................................................................. Package Dimensions ............................................................... Ball Pattern............................................................................... Recommended PC Board Characteristics ............................... 66 66 67 68 68 68 69 69 69 71 71 74 74 74 75 75 77 79 79 79 80 81 81 82 83 83 83 84 84 85 87 87 87 90 90 Appendix A: External Pins - - - - - - - - - - - - - - - - - 91 Appendix B: Recommended Heat Sinks - - - - - - - - - -121 Appendix C: Periphery Object Naming Convention - - - -125 2 Arrix Family Field Programmable Object Array (FPOA) www.mathstar.com Arrix Family Data Sheet www.DataSheet4U.com Table of Contents List of Figures Figure 1-1: FPOA Core and Periphery . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 1-2: FPOA Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 2-1: Ball Pattern for XRAM (Top-down View) . . . . . . . . . . 14 Figure 2-2: XRAM Clock Routing Option #1 . . . . . . . . . . . . . . . . . 22 Figure 2-3: XRAM Clock Routing Option #2 . . . . . . . . . . . . . . . . . 22 Figure 2-4: XRAM Clock to Data Clock Timing . . . . . . . . . . . . . . . 26 Figure 2-5: XRAM Address and Control Timing . . . . . . . . . . . . . . . 26 Figure 2-6: XRAM MRS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 2-7: XRAM Data Write Timing . . . . . . . . . . . . . . . . . . . . . . 27 Figure 2-8: XRAM Write Latency . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 2-9: XRAM Data Read Timing . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 2-10: XRAM Read Latency. . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 2-11: XRAM Write Followed By Read Timing . . . . . . . . . . 29 Figure 2-12: RLDRAM Initialization Sequence . . . . . . . . . . . . . . . . 33 Figure 3-1: Ball Pattern for GPIO (Top-down View). . . . . . . . . . . . 36 Figure 3-2: GPIO Input Timing (Synchronous) . . . . . . . . . . . . . . . . 41 Figure 3-3: GPIO Output Timing (Synchronous) . . . . . . . . . . . . . . . 41 Figure 3-4: GPIO Output Tri-state Timing . . . . . . . . . . . . . . . . . . . . 41 Figure 4-1: Ball Pattern for RX (Top-down View). . . . . . . . . . . . . . 44 Figure 4-2: RX DDR In-Phase Timing . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 4-3: RX DDR 90º Phase-Shifted Timing. . . . . . . . . . . . . . . . 49 Figure 4-4: RX SDR In-Phase Timing . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 4-5: RX SDR 90º Phase-Shifted Timing . . . . . . . . . . . . . . . . 49 Figure 5-1: Ball Pattern for TX (Top-down View). . . . . . . . . . . . . . 52 Figure 5-2: TX DDR In-Phase Timing . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 5-3: TX DDR 90º Phase-Shifted Timing. . . . . . . . . . . . . . . . 57 Figure 5-4: TX SDR In-Phase Timing . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 5-5: TX SDR 90º