Power MOSFET

www.DataSheet4U.com MGSF2P02HD Power MOSFET 2 Amps, 20 Volts P−Channel TSOP−6 This device represents a series of Power MOSFETs which are capable of withstanding high energy in the avalanche and commutation modes and the drain−to−source diode has a very low reverse recovery time. These devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc−dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. Features http://onsemi.com VDSS 20 V RDS(ON) TYP 175 mΩ ID MAX 2.0 A P−Channel 1256 3 • Miniature TSOP−6 Surface Mount Package − Saves Board Space • Low Profile for Thin Applications such as PCMCIA Cards • Very Low RDS(on) Provides Higher Efficiency and Expands • • • • • • Battery Life Logic Level Gate Drive − Can Be Driven by Logic ICs Diode is Characterized for Use in Bridge Circuits Diode Exhibits High Speed, with Soft Recovery IDSS Specified at Elevated Temperatures Avalanche Energy Specified Package Mounting Information Provided 1 TSOP−6 CASE 318G STYLE 1 4 MARKING DIAGRAM 3V W 3V W = Device Code = Work Week PIN ASSIGNMENT Drain Drain Source 6 5 4 1 2 3 Drain Drain Gate ORDERING INFORMATION Device MGSF2P02HDT1 MGSF2P02HDT3 Package TSOP−6 TSOP−6 Shipping† 3000 Tape & Reel 10,000 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2004 1 April, 2004 − Rev. 2 Publication Order Number: MGSF2P02HD/D MGSF2P02HD MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Drain−to−Source Voltage Drain−to−Gate Voltage (RGS = 1.0 MΩ) Gate−to−Source Voltage Drain Current − Continuous Drain Current − Single Pulse (tp ≤ 10 ms) Total Power Dissipation @ TC = 25°C Total Power Dissipation @ TC = 85°C Thermal Resistance − Junction to Ambient (Note 1.) Drain Current − Continuous Drain Current − Single Pulse (tp ≤ 10 ms) Total Power Dissipation @ TC = 25°C Total Power Dissipation @ TC = 85°C Thermal Resistance − Junction to Ambient (Note 2.) Operating and Storage Temperature Range Single Pulse Drain Source Avalanche Energy VDD = 20 V, VGS = 4.5 Vpk, IL = 3.6 Apk, L = 25 mH, RG = 25 W Symbol VDSS VDGR VGS ID IDM PD PD RqJA ID IDM PD PD RqJA TJ, Tstg EAS 160 °C Value 20 20 ±9 1.3 10 400 210 312 2.9 15 2.0 1.0 62.5 − 55 to 150 Unit V V V A mW mW °C/W A W W °C/W °C mJ THERMAL CHARACTERISTICS Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 5 seconds TL 260 1. Minimum FR−4 or G−10 PCB, Operating to Steady State. 2. Mounted onto a 2″ square FR−4 Board (1″ sq. 2 oz. Cu 0.06″ thick single sided), Operating time ≤5 seconds. http://onsemi.com 2 MGSF2P02HD ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Characteristic OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125°C) Gate−to−Source Leakage Current (VGS = ± 9.0 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 0.25 mAdc) Temperature Coefficient (Negative) Drain−to−Source On−Voltage (VGS = 4.5 Vdc, ID = 1.3 Adc) (VGS = 2.7 Vdc, ID = 0.8 Adc) Forward Transconductance (VDS = 10 Vdc, ID = 0.6 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Gate Charge (VDS = 16 Vdc, ID = 1.2 Adc, VGS = 4.5 Vdc) (VDD = 10 Vdc, ID = 0.6 Adc, VGS = 2.7 Vdc, 2 7 Vdc RG = 6.0 Ω) (VDS = 10 Vdc, ID = 1.2 Adc, VGS = 4.5 Vdc, 4 5 Vdc RG = 6.0 Ω) td(on) tr td(off) tf td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (IS = 1.2 Adc, VGS = 0 Vdc) Reverse Recovery Time (IS = 1.2 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) trr ta tb QRR NOTE: Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. VSD − − − − − − 0.89 0.72 86 27 59 0.115 1.1 − − − − − mC nsec Vdc − − − − − − − − − − − − 15 27 60 72 20 94 49 76 5.3 0.7 2.6 1.9 − − − − − − − − 7.5 − − − nC nsec (VDS = 15 Vdc, VGS = 0 Vdc, Vd Vd f = 1.0 MHz) Ciss Coss Crss − − − 225 150 60 − − − pF VGS(th) 0.7 − RDS(on) − − gFS 1.3 2.0 − 145 220 175 280 mhos 0.95 2.2 1.4 − Vdc mV/°C mW V(BR)DSS 20 IDSS − − IGSS − − − − 1.0 10 nAdc ± 100 − − mA Vdc Symbol Min Typ Max Unit http://onsemi.com 3 MGSF2P02HD TYPICAL ELECTRICAL CHARACTERISTICS 4.0 VGS = 8.0 V ID , DRAIN CURRENT (AMPS) 4.5 V 3.0 3.7 V 3.3 V 2.0 2.3 V 1.0 2.1 V 1.9 V 1.7 V 0 0 0.4 0.8 1.2 1.6 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 2.0 0 0 1.0 2.7 V 2.5 V 3.1 V 2.9 V ID , DRAIN CURRENT (AMPS) TJ = 25°C 3.0 4.0 VDS ≥ 10 V 2.0 1.0 100°C 25°C TJ = − 55°C 2.0 3.0 4.0 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS) Figure 2. Transfer Characteristics 0.4 0.6 TJ = 25°C 0.5 0.4 0.3 0.2 0.1 0 0 1.0 2.0 ID, DRAIN CURRENT (AMPS) 3.0 4.0 VGS = 2.7 V 0.3 ID = 1.3 A TJ = 25°C 0.2 0.1 4.5 V 0 0 2.0 4.0 6.0 8.0 10 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 3. On−Resistance versus Drain Current Figure 4. On−Resistance versus Drain Current and Gate Voltage RDS(on) , DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 2.0 VGS = 4.5 V ID = 0.8 A IDSS , LEAKAGE (nA) 1.5 100 TJ = 125°C 10 100°C 1.0 1.0 25°C VGS = 0 V 0.5 0 −50 − 25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) 0.1 0 4.0 8.0 12 16 20 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance versus Temperature Figure 6. Drain−To−Source Leakage Current versus Voltage http://onsemi.com 4 MGSF2P02HD POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG − VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) 800 Ciss C, CAPACITANCE (pF) 600 Crss 400 Ciss 200 Coss Crss 0 −10 VGS 0 VDS 10 20 VDS = 0 V VGS = 0 V TJ = 25°C The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation http://onsemi.com 5 MGSF2P02HD VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 5.0 QT 4.0 VDS VGS 16 20 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1000 VDD = 10 V ID = 1.2 A VGS = 4.5 V TJ = 25°C t, TIME (ns) 3.0 Q1 2.0 ID = 1.2 A TJ = 25°C Q3 0 0 1.0 2.0 3.0 4.0 5.0 QG, TOTAL GATE CHARGE (nC) Q2 12 100 tf td(off) tr td(on) 10 1.0 10 RG, GATE RESISTANCE (OHMS) 100 8.0 1.0