Configurable Octal Serial Switch

Freescale Semiconductor Advance Information Document Number: MC33880 Rev. 5.0, 6/2007 Configurable Octal Serial Switch with Serial Peripheral Interface I/O The 33880 device is an eight-output hardware-configurable highside/low-side switch with 8-bit serial input control. Two of the outputs can be controlled directly via microcontroller for Pulse Width Modulation (PWM) applications. The 33880 controls various inductive or incandescent loads by directly interfacing with a microcontroller. The circuit's innovative monitoring and protection features include very low standby currents, “cascadable” fault reporting, internal 40 V output clamping for low-side configurations, internal -20 V output clamping for high-side configurations, output-specific diagnostics, and independent shutdown of outputs. Features • Designed to Operate 5.5 V < VPWR < 24.5 V • 8-Bit SPI for Control and Fault Reporting, 3.3 V/ 5.0 V Compatible • Outputs Are Current Limited (0.8 A to 2.0 A) to Drive Incandescent Lamps • Output Voltage Clamp Is +45 V (Typical) (Low-Side Drive) and 20 V (Typical) (High-Side Drive) During Inductive Switching • Internal Reverse Battery Protection on VPWR • Loss of Ground or Supply Will Not Energize Loads or Damage IC • Maximum 5.0 µA IPWR Standby Current at 13 V VPWR up to 95°C • RDS(ON) of 0.55 Ω at 25°C Typical • Short Circuit Detect and Current Limit with Automatic Retry • Independent Overtemperature Protection • 32-Pin SOICW Has Pins 8, 9, 24, and 25 Grounded for Thermal Performance • Pb-Free Packaging Designated by Suffix Code EG and EW V PWR 5.0 V 5.0 V 33880 HIGH/LOW-SIDE SWITCH DW SUFFIX EG SUFFIX (PB-FREE) 98ASB42345B 28-PIN SOICW DWB SUFFIX EW SUFFIX (PB-FREE) 98ARH99137A 32-PIN SOICW ORDERING INFORMATION Device MC33880DW/R2 MCZ33880EG/R2 MC33880DWB/R2 MCZ33880EW/R2 28 SOICW -40°C to 125°C 32 SOICW Temperature Range (TA) Package www.DataSheet4U.com 33880 VPWR VDD D1 D2 D3 D4 D5 D6 D7 D8 S1 S2 S3 S4 S5 S6 S7 S8 VS High-Side EN MCU SPI I/O CS SCLK DI DO IN5 IN6 GND MOT H-Bridge PWM Low-Side All Output Switches are High- or Low-Side Configurable Figure 1. 33880 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2007. All rights reserved. INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM VDD __ CS SCLK DI DO OV, POR, SLEEP ~50 µA VPWR Overvoltage Shutdown/POR Sleep State Internal Bias Charge Pump GND EN ~50 µA SPI and Interface Logic SPI Bit 0 Typical of All 8 Output Drivers TLIM IN5 ~50 µA Enable SPI Bit 4 Gate Drive Control Current Limit Open Load Detect Current ~650 µA D1 D2 D3 D4 D7 D8 S1 S2 S3 S4 S7 S8 D5 D6 Drain Outputs IN6 ~50 µA IN5 + – + – Open/Short Comparator + _ ~1.5 V Open/Short Threshold Source Outputs TLIM Gate Drive Control Current Limit Open Load Detect Current ~650 µA Drain Outputs + – + – Open/Short Comparator + _ S5 S6 Source Outputs ~1.5 V Open/Short Threshold Figure 2. 33880 Simplified Internal Block Diagram 33880 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS GND VDD S8 S8 D8 S2 D2 S1 D1 D6 S6 IN6 EN SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 DO VPWR S7 S7 D7 S4 D4 S3 D3 D5 S5 IN5 CS DI Figure 3. 98ASB42345B SOICW 28-Pin Connections Table 1. SOICW 28-Pin Definitions Pin Number 1 2 3, 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25, 26 27 28 Pin Name GND VDD S8 D8 S2 D2 S1 D1 D6 S6 IN6 EN SCLK DI CS IN5 S5 D5 D3 S3 D4 S4 D7 S7 VPWR DO Digital ground. Logic supply voltage. Logic supply must be switched off for low current mode (VDD below 3.9 V). Output 8 MOSFET source pins. Output 8 MOSFET drain pin. Output 2 MOSFET source pin. Output 2 MOSFET drain pin. Output 1 MOSFET source pin. Output 1 MOSFET drain pin. Output 6 MOSFET drain pin. Output 6 MOSFET source pin. PWM direct control input pin for output 6. IN6 is “OR” with SPI bit. Enable input. Allows control of outputs. Active high. SPI control clock input pin. SPI control data input pin from MCU to the 33880. Logic [1] activates output. SPI control chip select input pin from MCU to the 33880. Logic [0] allows data to be transferred in. PWM direct control input pin for output 5. IN5 is “OR” with SPI bit. Output 5 MOSFET source pin. Output 5 MOSFET drain pin. Output 3 MOSFET drain pin. Output 3 MOSFET source pin. Output 4 MOSFET drain pin. Output 4 MOSFET source pin. Output 7 MOSFET drain pin. Output 7 MOSFET source pins. Power supply pin to the 33880. VPWR has internal reverse battery protection. SPI control data output pin from the 33880 to the MCU. DO = 0 no fault, DO = 1 specific output has fault. Definition 33880 Analog Integrated Circuit Device Data Freescale Semiconductor 3 PIN CONNECTIONS GND VDD S8 S8 D8 S2 D2 GND GND S1 D1 D6 S6 IN6 EN SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 DO VPWR S7 S7 D7 S4 D4 GND GND S3 D3 D5 S5 IN5 CS DI Figure 4. 98ARH99137A SOICW 32-Pin Connections Table 2. SOICW 32-Pin Definitions Pin Number 1, 8, 9, 24, 25 2 3, 4 5 6 7 10 11 12 13 14 15 16 17 18 19 20 21 22 23 26 27 28 29, 30 31 32 Pin Name GND VDD S8 D8 S2 D2 S1 D1 D6 S6 IN6 EN SCLK DI CS IN5 S5 D5 D3 S3 D4 S4 D7 S7 VPWR DO Digital ground. Logic supply voltage. Logic supply must be switched off for low current mode (VDD below 3.9 V). Output 8 MOSFET source pins. Output 8 MOSFETdrain pin. Output 2 MOSFET source pin. Output 2 MOSFET drain pin. Output 1 MOSFET source pin. Output 1 MOSFET drain pin. Output 6 MOSFETdrain pin. Output 6 MOSFET source pin. PWM direct control input pin for output 6. IN6 is “OR” with SPI bit. Enable input. Allows control of outputs. Active high. SPI control clock input pin. SPI control data input pin from MCU to the 33880. Logic [1] activates output. SPI control chip select input pin from MCU to the 33880. Logic [0] allows data to be transferred in. PWM direct control input pin for output 5. IN5 is “OR” with SPI bit. Output 5 MOSFET source pin. Output 5 MOSFET drain pin. Output 3 MOSFET drain pin. Output 3 MOSFET source pin. Output 4 MOSFET drain pin. Output 4 MOSFET source pin. Output 7 MOSFET drain pin. Output 7 MOSFET source pins. Power supply pin to the 33880. VPWR has internal reverse battery protection. SPI control data output pin from the 33880 to the MCU. DO = 0 no fault, DO = 1 specific output has fault. Definition 33880 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 3. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings VDD Supply Voltage (1) CS, DI, DO, SCLK, IN5, IN6, and EN (1) VPWR Supply Voltage (1) Drain 1 – 8 (2) 5.0 mA ≤ IOUT ≤ 0.3 A Source 1 – 8 (3) 5.0 mA ≤ IOUT ≤ 0.3 A Output Voltage Clamp Low-Side Drive (4) Output Voltage Clamp High-Side Drive (4) Output Clamp Energy (5) ESD Voltage (6) Human Body Model Machine Model Storage Temperature Operating Case Temperature Operating Junction Temperature Maximum Junction Temperature Power Dissipation (TA = 25°C) 28 SOIC, Case 751F-05 32 SOIC, Case 1324-02 Thermal Resistance, Junction-to-Ambient, 28 SOIC, Case 751F-05 Thermal Resistance, Junction-to-Ambient, 32 SOIC, Case 1324-02 Thermal Resistance, Junction-to-Thermal Ground Leads, 32 SOIC, Case 1324-02 Peak Package Reflow Temperature During Reflow (5), (6) Notes 1. 2. 3. 4. 5. 6. 7. RθJA RθJA RθJL TPPRT (7) Symbol VDD – VPWR – Value -0.3 to 7.0 -0.3 to 7.0 -16 to 50 Unit VDC VDC VDC VDC -18 to 40 – -28 to 40 VOC VOC ECLAMP 40 to 55 -15 to -25 50 VDC VDC mJ V VESD1 VESD2 TSTG TC TJ – PD 1.3 1.7 94 70 18 Note 6 °C ±2000 ±200 -55 to 150 -40 to 125 -40 to 150 -40 to 150 VDC °C °C °C °C W °C/W °C/W Exceeding these limits may cause malfunction or permanent damage to the device. Configured as low-side driver with 300 mA load as current limit. Configured as high-side driver with 300 mA load as current limit. With outputs OFF and 10 mA of test current for low-side driver, 30 mA test current for high-side driver. Maximum output clamp energy capability at 150°C junction temperature using single non-repetitive pulse method. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), and ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω). Maximum power dissipation with no heatsink used. 33880 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TC ≤ 125°C unless otherwise noted. Typical values, where applicable, reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C. Characteristic POWER INPUT Supply Voltage Range Fully Operational Supply Current Sleep State Supply Current (VDD and EN = 0 V, VPWR = 16 V) Temperature = -40°C to 95°C Temperature = 95°C to 125°C Overvoltage Shutdown Overvoltage Shutdown Hysteresis Logic Supply Voltage Logic Supply Current Logic Supply Undervoltage Lockout Threshold Logic Supply Undervoltage Hysteresis POWER OUTPUT Drain-to-Source ON Resistance (VPWR = 16 V) IOUT = 0.25 A, TJ = 125°C IOUT = 0.25 A, TJ = 25°C IOUT = 0.25 A, TJ = -40°C Output Self-Limiting Current High-Side and Low-Side Configurations VPWR = 16 V Output Fault Detect Threshold (8), (9) Outputs Programmed OFF Output Off Open Load Detect Current (8) Outputs Programmed OFF Output Clamp Voltage Low-Side Drive ID = 10 mA Output Clamp Voltage High-Side Drive IS = -30 mA Output Leakage